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IEEE Micro

Issue 1 • Jan.-Feb. 2005

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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    Freely Available from IEEE
  • Masthead

    Publication Year: 2005, Page(s): 4
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    Freely Available from IEEE
  • The "power" of communication

    Publication Year: 2005, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB) | HTML iconHTML

    Welcome to IEEE Micro's first issue of 2005. Like last year, we begin with a theme issue on Hot Interconnects. In addition to this main theme, the issue also contains two other important articles dealing with mainstream microprocessor architectures. View full abstract»

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  • FTC cracks down on spyware and PC hijacking, but not true lies

    Publication Year: 2005, Page(s):6 - 7, 100-1
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    The US Federal Trade Commission (FTC) recently sued an Internet marketing organization to make it stop infecting consumers' PCs with spyware. According to the FTC, Seismic Entertainment Productions developed a scheme that seized control of PCs nationwide, infected them with spyware and other malicious software, bombarded them with a barrage of pop-up advertising for Seismic's clients, exposed the ... View full abstract»

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  • Guest Editors' Introduction: Hot Interconnects 12

    Publication Year: 2005, Page(s):8 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    Hot Interconnects is an annual conference that specializes in state-of-the-art hardware and software architectures, and implementations of interconnection networks of all scales, ranging from on-chip, processor-memory interconnects to wide-area networks. It is the event where the high-performance computing and high-speed networking communities meet, and has a wide attendance both from industry and... View full abstract»

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  • Localized congestion control in advanced switching interconnects

    Publication Year: 2005, Page(s):10 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    The PCI Express advanced switching interconnect architecture includes status-based flow control (SBFC), a localized congestion-control mechanism that aims to alleviate the effects of transient congestion. The SBFC scheme suffices for handling persistent congestion in single-stage switch fabrics and complements traditional congestion management schemes in larger switch. View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2005, Page(s): 19
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  • Evaluating InfiniBand performance with PCI Express

    Publication Year: 2005, Page(s):20 - 29
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    The InfiniBand architecture is an industry standard that offers low latency and high bandwidth as well as advanced features such as remote direct memory access (RDMA), atomic operations, multicast, and quality of service. InfiniBand products can achieve a latency of several microseconds for small messages and a bandwidth of 700 to 900 Mbytes/s. As a result, it is becoming increasingly popular as a... View full abstract»

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  • Performance evaluation of the Cray X1 distributed shared-memory architecture

    Publication Year: 2005, Page(s):30 - 40
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1's distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. In this arti... View full abstract»

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  • Design of a high-speed optical interconnect for scalable shared-memory multiprocessors

    Publication Year: 2005, Page(s):41 - 49
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    Large-scale distributed shared-memory multiprocessors (DSMs) provide a shared address space by physically distributing the memory among different processors. A fundamental DSM communication problem that significantly affects scalability is an increase in remote memory latency as the number of system nodes increases. Remote memory latency, caused by accessing a memory location in a processor other ... View full abstract»

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  • Efficient multimatch packet classification and lookup with TCAM

    Publication Year: 2005, Page(s):50 - 59
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Today's packet classification systems are designed to provide the highest-priority matching result, such as the longest prefix match, even if a packet matches multiple classification rules. However, new network applications demanding multimatch classification - that is, requiring all matching results instead of only the highest-priority match - are emerging. Ternary content-addressable memory is b... View full abstract»

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  • A hardware-accelerated system for real-time worm detection

    Publication Year: 2005, Page(s):60 - 69
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    Internet worms work by exploiting vulnerabilities in operating systems and application software that run on end systems. The attacks compromise security and degrade network performance. They cause large economic losses for businesses, in terms of system downtime and lost worker productivity. This article presents the design and implementation of a system that automatically detects new worms in rea... View full abstract»

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  • Using hardware to configure a load-balanced switch

    Publication Year: 2005, Page(s):70 - 78
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    Efficient router architectures should have predictable throughput and scalable capacity, as well as internal optical technology (such as optical switches and wavelength division multiplexing) that can increase capacity by reducing power consumption. The load-balanced switch is a promising way to scale router capacity. In this 100-terabit-per-second router, an optical switch spreads traffic evenly ... View full abstract»

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  • Better branch prediction through prophet/critic hybrids

    Publication Year: 2005, Page(s):80 - 89
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    The prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch future. The critic uses the branch's history and future to critique the prophet's prediction. The hybrid combines the prophet's prediction with the critique, either agrees or disa... View full abstract»

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  • Data cache prefetching using a global history buffer

    Publication Year: 2005, Page(s):90 - 97
    Cited by:  Papers (16)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Over the past couple of decades, trends in both microarchitecture and underlying semiconductor technology have significantly reduced microprocessor clock periods. These trends have significantly increased relative main-memory latencies as measured in processor clock cycles. To avoid large performance losses caused by long memory access delays, microprocessors rely heavily on a hierarchy of cache m... View full abstract»

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  • Too much information

    Publication Year: 2005, Page(s):98 - 99
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    Freely Available from IEEE
  • Not a mellifluous march to maturity [computer market]

    Publication Year: 2005, Page(s):104, 102 - 103
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (83 KB) | HTML iconHTML

    The maturity of the computer market is discussed. There are three distinct types of maturity - technical, market, and organizational - and they neither relate to one another in a straightforward way nor do they relate to restructuring. That obscures a second and deeper problem. Restructuring can lead to bitter losses for employees. View full abstract»

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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center