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Solid-State Circuits, IEEE Journal of

Issue 3 • Date March 2005

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Displaying Results 1 - 25 of 37
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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  • Table of contents

    Page(s): 573 - 574
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  • New Associate Editor

    Page(s): 575
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  • A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology

    Page(s): 576 - 583
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    The design of a high-voltage output driver in a digital 0.25-μm 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-Ω load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 Ω. View full abstract»

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  • Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

    Page(s): 584 - 592
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    Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-μm CMOS amplifiers, SMC, and SMFFC driving a 25-kΩ//120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a ±1-V power supply, and each occupies less than 0.02 mm2 of silicon area. View full abstract»

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  • A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

    Page(s): 593 - 602
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    This paper presents a CMOS 0.25-μm continuous-time 6-tap FIR filter that is used as a fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter delay line is realized with a second-order low-pass filter. Simulations show that the tap delay can be tuned from 100 ps to 300 ps while keeping a constant group delay within the bandwidth of 2.1 GHz and 800 MHz correspondingly. Experimental results show that the FIR filter can successfully recover a 1-Gb/s differential digital signal that has been transmitted over a 220-inch PCB trace which causes -31.48-dB attenuation at the symbol rate frequency of 1 GHz. The measured bit error rate after equalization is less than 10-12 over a 750-ps sampling range, compared to a 10-2 bit-error rate before equalization. Also presented are the measurement results comparing the horizontal and the vertical openings of the signals before and after equalization for PCB traces with different length. The chip dissipates 45 mW from a 2.5-V supply and occupies 0.33×0.27 mm2 in a 0.25-μm CMOS process. View full abstract»

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  • A 2-GS/s 3-bit ΔΣ-modulated DAC with tunable bandpass mismatch shaping

    Page(s): 603 - 610
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    Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, ΔΣ-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass ΔΣ modulators to dynamically route the digital signals to the DACs. These ΔΣ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption. View full abstract»

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  • A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control

    Page(s): 611 - 621
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    This paper presents the design and measured performance of a 1.8-GHz power amplifier featuring load mismatch protection and soft-slope power control. Load-mismatch-induced breakdown can be avoided by attenuating the RF power to the final stage during overvoltage conditions. This was accomplished by means of a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. The issue of output power control has been addressed as well. To this end, a temperature-compensated bias network is proposed, which allows a moderate power control slope (dB/V) to be achieved by varying the circuit quiescent current according to an exponential law. The nonlinear power amplifier was fabricated using a low-cost silicon bipolar process with a 6.4-V breakdown voltage. It delivers a 33.5-dBm saturated output power with 46% maximum power-added efficiency and 36-dB gain at a nominal 3.5-V supply voltage. The device is able to tolerate a 10:1 load standing-wave ratio up to a 5.1-V supply voltage. Power control slope is lower than 80 dB/V between -15 dBm and the saturated output power level. View full abstract»

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  • A monolithic double-balanced direct conversion mixer with an integrated wideband passive balun

    Page(s): 622 - 629
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    This paper presents the design and performance characteristics of a 20-40 GHz monolithic double-balanced direct conversion mixer implemented using InGaP/GaAs HBT process. The compact MMIC mixer makes use of a Gilbert-cell multiplier and utilizes a broadband monolithic passive balun that has been developed for MMIC applications. The new balun makes use of multidielectric layer structure to achieve a broadband performance in a simple coplanar configuration. A measured return loss better than 15 dB, with a maximum insertion loss of 4.5 dB including the 3-dB power splitting loss has been achieved over the band from 15 to 45 GHz. Operated as a downconverter mixer, the newly developed direct conversion mixer achieves a measured conversion gain of 16 dB given an RF signal at 30 GHz, LO drive of 5 dBm and a downconverted baseband signal at 10 MHz. The mixer IP3 occurs at an output power of 4 dBm while the IP2 occurs at an output power of 11 dBm. View full abstract»

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  • Minimum achievable phase noise of RC oscillators

    Page(s): 630 - 637
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    To make RC oscillators suitable for RF applications, their typically poor phase-noise characteristics must be improved. We show that, for a given power consumption, this improvement is fundamentally limited by the fluctuation-dissipation theorem of thermodynamics. We also present the analytical formulation of this limit for relaxation (including ring) oscillators using a time-domain phase-noise analysis method which is introduced in this paper. Measurement shows the maximum possible improvement is generally less than 6dB for ring oscillators, while it can be as high as 21dB for other relaxation oscillators. The suboptimal performance of relaxation oscillators is attributed to the continuous current flow in these oscillator topologies. These results provide useful insight for feasibility studies of oscillator design. View full abstract»

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  • Standing wave oscillators utilizing wave-adaptive tapered transmission lines

    Page(s): 638 - 651
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    In this paper, we introduce a novel standing wave oscillator (SWO) utilizing standing-wave-adaptive tapered transmission lines. This structure enhances Q and lowers phase noise through loss-reducing shaping of the transmission line, such that it is adapted to the position-dependent amplitudes of standing waves. Measurements validate the advantages of the proposed technique. The phase noise of a MOS SWO with the tapered line is 5-10 dB less than that of a uniform-line MOS SWO over a wide range of offset frequencies, centered about 15 GHz. Demonstrating a valuable exploitation of standing wave properties, the novel design concept boosts the potential for the emergence of standing wave oscillators as a useful alternative to the traditional lumped LC oscillator. View full abstract»

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  • Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback

    Page(s): 652 - 660
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    A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-μm CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 μW and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage. View full abstract»

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  • A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

    Page(s): 661 - 670
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    An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-μm CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively. View full abstract»

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  • A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range

    Page(s): 671 - 677
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    A microwatt frequency divider for the 2.5-GHz ISM band is proposed. This divider directly modulates the output in a ring oscillator by means of a switch and realizes low power consumption with low supply voltage and a wide locking range. It is fabricated using a five-layer-metal and 0.2-μm-gate length CMOS process. The core size is 10.8×10.5 μm2, which is much smaller than that of a typical inductor-enhanced frequency divider. This divider operates with a supply voltage in the range from 1.8 to 0.7V, and attains minimum power consumption of 44 μW, in which case the supply voltage is 0.7 V, the maximum operating frequency is 4.3 GHz, and the locking range is 2.3 GHz. A derivation of the frequency locking range of the divider is provided in the Appendix. View full abstract»

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  • A multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC

    Page(s): 678 - 689
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    This work presents a shared fractional-N synthesizer used by two dual-band 802.11 radios integrated on a single chip for 2×2 multiple-input multiple-output (MIMO) applications. Additional 2×2 MIMO chips can be used in a system by phase synchronizing the signal paths through a bidirectional LO porting scheme developed for this application. This synthesizer was fully integrated with the exception of an off-chip loop filter. The synthesizer is a ΔΣ-based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in the IEEE 802.11a/b/g and Japanese WLAN standards. The radio uses a variable IF frequency so that both the RF LO and IF LO can be derived from a single synthesizer saving chip area and power. The synthesizer includes a programmable second/third-order ΔΣ noise shaper, a phase frequency detector, a differential charge pump, and a 6-bit multimodulus divider (MMD). The nominal jitter from 100 Hz to 10 MHz is 0.63-0.86° rms in the 5-GHz band and 0.35-0.43° rms in the 2.4-GHz band. The maximum frequency deviation of the synthesizer when enabling the transmitter is less than 150 kHz and the frequency error settles to 2 kHz in less than 12 μs. For MIMO applications requiring more than two full paths, a single synthesizer on one die can be used to generate the LOs for all other radios integrated in different dies. View full abstract»

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  • A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications

    Page(s): 690 - 697
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    Employing feedback circuits in RF front-ends can be a key aspect for easy reconfiguration of multistandard receivers. A narrow-band filter can shape the frequency transfer function and, by reflection due to the feedback network, the input impedance. Switching one single filter component thus allows selecting a different standard. We introduce a voltage-voltage feedback low noise amplifier that, besides being easily reconfigurable, shows roughly the same noise and better linearity, for same power consumption, as the conventional inductively degenerated topology. A direct conversion front-end, including the LNA and I and Q mixers, tailored to WLAN applications in the 5-6 GHz range, has been realized in a 0.25-μm SiGe BiCMOS process. Prototypes show the following performances: 2.5 dB NF, 31.5 dB gain, -9.5dBm IIP3, and +23dBm minimum IIP2 while consuming 16 mA from a 2.5 V supply. View full abstract»

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  • A dual-mode 802.11b/bluetooth radio in 0.35-μm CMOS

    Page(s): 698 - 706
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    A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps. View full abstract»

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  • A transmitter IC for TETRA systems based on a Cartesian feedback loop linearization technique

    Page(s): 707 - 718
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    A fully integrated linearized transmitter for the next generation TETRA systems for PMR and public safety applications in a CMOS-based SiGe technology is described. The presented single-chip transmitter employs a Cartesian feedback loop technique in order to improve the linearity of the externally connected power amplifier. The transmitter is usable in a frequency range from 300 MHz up to 800 MHz, providing a linearity improvement of more than 40 dB. View full abstract»

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  • A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

    Page(s): 719 - 725
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    A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance is proposed. BIGCAP is composed of a pair of accumulation-mode n-poly gate capacitors in an n-well and a pair of pMOS gate capacitors, which requires no additional fabrication process steps. Measured results with 1.5-V 0.13-μm digital CMOS technology show that the intrinsic capacitance is 6.7 fF/μm2 (6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is ±2.9% and capacitance variation across a wafer is as small as σ= 0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only σ= 0.69% and the linearity ranged from ±2.84% to ±2.93%. For three types of BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than ±4% linearity is achievable by optimizing the ratio (x) of the pMOS gate capacitors' area to the area of the n-poly gate capacitors, and the optimum x value is within a range of 15%-25%. BIGCAP has been applied to the loop filter of a differential phase-locked loop (PLL) and reduces the gate area of the largest loop filter capacitor to only 35% of that of the conventional design while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps (peak-to-peak) at 840 MHz with a 1.5-V supply. View full abstract»

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  • Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

    Page(s): 726 - 735
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    Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF50 and NFmin are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs. View full abstract»

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  • A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

    Page(s): 736 - 743
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    This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-μm CMOS technology the module has a size of 0.25×1.4 mm2. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 223-1 and a bit-error rate threshold of 10-12. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s. View full abstract»

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  • Nonlinear transmission lines for pulse shaping in silicon

    Page(s): 744 - 752
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    Nonlinear transmission lines (NLTL) are used for pulse shaping. We developed the theory of pulse propagation through the NLTL. The problem of a wide pulse degenerating into multiple pulses rather than a single pulse is solved by using a gradually scaled NLTL. We exploit certain favorable properties of accumulation-mode MOS varactors to design an NLTL that can simultaneously sharpen both rising and falling edges. There is a good agreement among the theory, simulations, and measurements. View full abstract»

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  • A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

    Page(s): 753 - 762
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    This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-μm CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone). View full abstract»

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  • A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device

    Page(s): 763 - 771
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    This paper reports a driver circuitry to generate bi-phasic (anodic and cathodic) current pulses for stimulating the retinal layer through electrodes which is part of a retinal prosthetic device for implants in blind patients affected by retinitis pigmentosa (RP) and age-related macular degeneration (AMD). Dual voltage architecture is used to halve the number of interface leads from the chip to the stimulation sites compared to a single voltage supply. The driver circuitry is designed to deliver currents with six bit resolution for a wide range of full scale currents up to 600 μA. To cater to the varying stimulus requirements among patients and different regions of the retina, variable gain architecture is used to achieve fine resolution even for a narrow range of stimulus. 1:8 demultiplexing feature is embedded within the output stage thus allowing one DAC for eight outputs. A novel charge cancellation circuitry with current limiting capability is implemented to discharge the electrodes for medical safety. Measurement results of a prototype chip fabricated in 1.5-μm CMOS technology are presented. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan