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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 12 • Date Dec. 2004

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Editorial the responsibility of reviewers

    Publication Year: 2004, Page(s):1261 - 1262
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  • SOC test planning using virtual test access architectures

    Publication Year: 2004, Page(s):1263 - 1276
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (837 KB) | HTML iconHTML

    Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to gigahertz speeds. However, system-on-chip (SOC) scan chains are typically run at lower frequencies, e.g., 10-50 MHz. The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in SOC testing time. We present a new ... View full abstract»

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  • Weighted pseudorandom hybrid BIST

    Publication Year: 2004, Page(s):1277 - 1283
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB) | HTML iconHTML

    This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces te... View full abstract»

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  • Online BIST and BIST-based diagnosis of FPGA logic blocks

    Publication Year: 2004, Page(s):1284 - 1294
    Cited by:  Papers (31)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (475 KB) | HTML iconHTML

    We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs... View full abstract»

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  • Power characteristics of inductive interconnect

    Publication Year: 2004, Page(s):1295 - 1306
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB) | HTML iconHTML

    The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeo... View full abstract»

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  • Efficient simulation of nonuniform transmission lines using integrated congruence transform

    Publication Year: 2004, Page(s):1307 - 1320
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB) | HTML iconHTML

    This paper presents a new algorithm based on integrated congruence transform for efficient simulation of nonuniform transmission lines. The proposed algorithm introduces the concept of model-order reduction (MOR) via implicit usage of the Hilbert-space moments in distributed networks. The key idea in the proposed algorithm is the development of an orthogonalization procedure that does not require ... View full abstract»

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  • Differential current-sensing for on-chip interconnects

    Publication Year: 2004, Page(s):1321 - 1329
    Cited by:  Papers (19)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increa... View full abstract»

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  • Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models

    Publication Year: 2004, Page(s):1330 - 1347
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1753 KB) | HTML iconHTML

    Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However... View full abstract»

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  • Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

    Publication Year: 2004, Page(s):1348 - 1359
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB) | HTML iconHTML

    This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay incr... View full abstract»

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  • Cascaded Bayesian inferencing for switching activity estimation with correlated inputs

    Publication Year: 2004, Page(s):1360 - 1370
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB) | HTML iconHTML

    In this paper, we investigate the estimation of switching activity in VLSI circuits using a graphical probabilistic model based on cascaded Bayesian networks (CBNs). First, we develop a theoretical analysis for Bayesian inferencing of switching activity and then derive upper bounds for certain circuit parameters which, in turn, are useful in establishing the cascade structure of the CBN model. We ... View full abstract»

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  • Routability checking for three-dimensional architectures

    Publication Year: 2004, Page(s):1371 - 1374
    Cited by:  Papers (11)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB) | HTML iconHTML

    We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and de... View full abstract»

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  • Bus-switch coding for reducing power dissipation in off-chip buses

    Publication Year: 2004, Page(s):1374 - 1377
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB) | HTML iconHTML

    We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle... View full abstract»

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  • A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

    Publication Year: 2004, Page(s):1377 - 1381
    Cited by:  Papers (15)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area ... View full abstract»

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  • Sequence-switch coding for low-power data transmission

    Publication Year: 2004, Page(s):1381 - 1385
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    Reducing the power dissipated by buses becomes one of the most important elements in low-power VLSI design. A new coding scheme called sequence-switch coding (SSC) is proposed in this paper. It is a general-purpose coding scheme that employs the sequence of data in reducing the number of transitions on buses. A simple switching algorithm is presented to show the feasibility of SSC. According to si... View full abstract»

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  • Fault isolation for nonisolated blocks

    Publication Year: 2004, Page(s):1385 - 1388
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (202 KB) | HTML iconHTML

    We consider circuits represented as interconnections of logic blocks. In such circuits, the goal of fault isolation is to identify which one of the blocks is faulty based on a faulty output response produced by the circuit. We study this issue and demonstrate that perfect or close-to-perfect fault isolation is possible with tests that propagate fault effects through pairs of blocks. We relate this... View full abstract»

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  • List of Reviewers

    Publication Year: 2004, Page(s):1389 - 1391
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1392
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  • 2004 Index

    Publication Year: 2004, Page(s):1393 - 1411
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  • Explore IEL IEEE's most comprehensive resource

    Publication Year: 2004, Page(s): 1412
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu