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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 3 • March 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • POMR: a power-aware interconnect optimization methodology

    Publication Year: 2005, Page(s):297 - 307
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB) | HTML iconHTML

    As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect bu... View full abstract»

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  • Optimization of throughput performance for low-power VLSI interconnects

    Publication Year: 2005, Page(s):308 - 318
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (481 KB) | HTML iconHTML

    The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and s... View full abstract»

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  • Extended global routing with RLC crosstalk constraints

    Publication Year: 2005, Page(s):319 - 329
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB) | HTML iconHTML

    In this paper, we study an extended global routing problem with RLC crosstalk constraints. Considering simultaneous shield insertion and net ordering, we propose a multiphase algorithm to synthesize a global routing solution with track assignment to satisfy the RLC crosstalk constraint at each sink. The key algorithm phase is global routing synthesis with shield reservation and minimization based ... View full abstract»

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  • Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

    Publication Year: 2005, Page(s):330 - 338
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (601 KB) | HTML iconHTML

    A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal I... View full abstract»

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  • On the impact of on-chip inductance on signal nets under the influence of power grid noise

    Publication Year: 2005, Page(s):339 - 348
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1609 KB) | HTML iconHTML

    It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence ... View full abstract»

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  • A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

    Publication Year: 2005, Page(s):349 - 357
    Cited by:  Papers (48)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (723 KB) | HTML iconHTML

    This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to bui... View full abstract»

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  • Design of a 3-D fully depleted SOI computational RAM

    Publication Year: 2005, Page(s):358 - 369
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1194 KB) | HTML iconHTML

    We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physica... View full abstract»

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  • Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis

    Publication Year: 2005, Page(s):370 - 383
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1193 KB) | HTML iconHTML

    This paper presents a novel input test buffer design methodology that is used for testing the differential signaling interconnects. The input test buffer is aimed to detect hardware failures in differential electrical connections. The input test buffer can also be used to check the differential signal's connectivity such as, diagnosing the cable connections, detecting off-lined or un-powered conne... View full abstract»

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  • Low-power scan design using first-level supply gating

    Publication Year: 2005, Page(s):384 - 395
    Cited by:  Papers (63)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (717 KB) | HTML iconHTML

    Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in comb... View full abstract»

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  • Shielding effect of on-chip interconnect inductance

    Publication Year: 2005, Page(s):396 - 400
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the over... View full abstract»

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  • Efficient shield insertion for inductive noise reduction in nanometer technologies

    Publication Year: 2005, Page(s):401 - 405
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy... View full abstract»

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  • A temperature-insensitive self-recharging circuitry used in DRAMs

    Publication Year: 2005, Page(s):405 - 408
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB) | HTML iconHTML

    This paper presents a practical self-recharging circuitry for DRAMs. The proposed self-recharging circuitry not only reduces the standby power by monitoring the voltage drop caused by the data loss of a memory cell but also adjusts the recharging period of the memory cell that results from leakage currents. The proposed design is insensitive to temperature variations. A 1-Kb DRAM using our design ... View full abstract»

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  • Erratum

    Publication Year: 2005, Page(s): 409
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  • International Symposium on Low Power Electronics and Design (ISLPED'05)

    Publication Year: 2005, Page(s): 410
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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 411
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  • IEEE order form for reprints

    Publication Year: 2005, Page(s): 412
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu