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IEEE Potentials

Issue 1 • Date Feb.-March 2005

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Displaying Results 1 - 21 of 21
  • The conference low-down

    Publication Year: 2005, Page(s): 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB) | HTML iconHTML

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  • The smart medical refrigerator

    Publication Year: 2005, Page(s):42 - 45
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB) | HTML iconHTML

    This work presents a smart medical refrigerator. The method suggests to monitor the elderly patients continued usage of medications on time. So a smart medical dispenser is used. The smart medical refrigerator monitors the use of prescribed medicine by patients and can alert a physician, healthcare provider or family members if the patient does not access the medicine in a set time frame. The smar... View full abstract»

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  • Circuit modeling in high-speed designs

    Publication Year: 2005, Page(s):17 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB) | HTML iconHTML

    This work presents the design and modeling of highspeed circuits. Modeling of high-speed circuits is usually divided into physical and behavioral representations. Physical modeling is the actual transistor level design of the high-speed chip or circuit for inter-chip communications and system level simulations. Behavioral modeling imitates the behavior of the circuit when various input/output cond... View full abstract»

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  • Mixed mode integrated circuits

    Publication Year: 2005, Page(s):6 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1450 KB) | HTML iconHTML

    This work presents the mixed mode integrated circuit design. The development of SOC technology, CAD and simulation resources are providing system and chip designers with design tools necessary for successfully completing fully integrated CMOS hardware. The design methodology and new CAD/simulation tools allow the design engineer to focus on the mixed mode integrated circuit design without losing c... View full abstract»

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  • Reversible logic

    Publication Year: 2005, Page(s):38 - 41
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (838 KB) | HTML iconHTML

    This work presents the logical reversibility. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations can't erase information and dissipate zero heat. The circuit actually operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power. As the basic elements of any logic circuit, logic ga... View full abstract»

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  • Automatic test generation for verifying microprocessors

    Publication Year: 2005, Page(s):34 - 37
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (618 KB) | HTML iconHTML

    A pipelined processor with a high-level behavioral HDL description is presented in this paper. It generates a set of effective test programs by using a simulator, which is able to evaluate with respect to an RTL coverage metric. The proposed optimizer is based on a technique called microGP, an evolutionary system able to automatically device and optimizes the program written in an assembly languag... View full abstract»

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  • Modeling ESD protection

    Publication Year: 2005, Page(s):21 - 24
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB) | HTML iconHTML

    This work presents the modeling and simulation of ESD circuit design protection. The electrostatic discharge (ESD) is a charge rebalancing process between two adjacent ICs. The ESD can cause IC failure during the manufacturing, the testing, the handling and the assembly of integrated circuits (ICs). ESD protection design methodology needs to be as systematic and transferable as possible. The empir... View full abstract»

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  • An embedding debugging architecture for SOCs

    Publication Year: 2005, Page(s):12 - 16
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2702 KB) | HTML iconHTML

    Multiple cores embedded debugging architecture for system on chip design (SOC) is presented. It presents an asymmetrical functional test problem. To analyze the problem and optimize performance in multicore operation, debug tools with interfaces are exercised for several cores. HyperJTAG (joint test action group) interface reduces the IO pin interfaces required for debugging several cores. To over... View full abstract»

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  • 2005 Student Activities Committee e-mail addresses

    Publication Year: 2005, Page(s): 47
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  • Essay - Examining the possibilities

    Publication Year: 2005, Page(s): 5
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  • A survey contactless measurement and testing techniques

    Publication Year: 2005, Page(s):25 - 28
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (634 KB) | HTML iconHTML

    Electron-beam testing technique includes photoemissive probing; electrooptic sampling; charge density probing and photoexcitation are analyzed. Among these techniques an ideal contactless probing system is simple, inexpensive to operate and compatible with the existing test equipment. It will not perturb the circuit and would measure electric signals with minimum crosstalk. Experimental results de... View full abstract»

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  • Processor validation: a top-down approach

    Publication Year: 2005, Page(s):29 - 33
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1006 KB) | HTML iconHTML

    This work presents the design validation techniques for microprocessors. The verification effectiveness validates the design implementation using a combination of simulation techniques and formal methods. This article presents a top-down validation methodology that complements existing bottom-up verification techniques. The validation team applies model checking to a high-level description of the ... View full abstract»

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  • IEEE Potentials

    Publication Year: 2005, Page(s): 0_1
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    Freely Available from IEEE
  • Now you can...Xplore - IEEE

    Publication Year: 2005, Page(s): 02
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  • Table of contents

    Publication Year: 2005, Page(s): 1
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  • IEEE Potential's Staff List

    Publication Year: 2005, Page(s): 2
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  • Editorial

    Publication Year: 2005, Page(s): 3
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  • Finding your dream job - IEEE

    Publication Year: 2005, Page(s): 4
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  • Gamesman problems / Gamesman solutions

    Publication Year: 2005, Page(s):48 - 47
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  • GOLD - Graduates of the Last Decade - IEEE online

    Publication Year: 2005, Page(s): 03
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  • Renew your IEEE membership for 2005

    Publication Year: 2005, Page(s): 04
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Aims & Scope

IEEE Potentials is the magazine dedicated to undergraduate and graduate students and young professionals.

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Meet Our Editors

Editor-in-Chief
Sachin Seth
Texas Instruments
sachin3006@gmail.com