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Computers and Digital Techniques, IEE Proceedings -

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Computers and Digital Techniques, IEE Proceedings -

Issue 1 • Date 14 Jan. 2005

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Title History

Editorial

System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

Testable synthesis of synchronous sequential circuits considering strong-connectivity using undefined states

Architecture-level performance estimation method based on system-level profiling

Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems

Unified SOC test approach based on test data compression and TAM design

Redundancy modelling and array yield analysis for repairable embedded memories

Compression considerations in test access mechanism design

Emerging strategies for resource-constrained testing of system chips

Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures

Resource-constrained system-on-a-chip test: a survey

Noisy signal based background technique for gain error correction in pipeline ADCs

Phase-frequency transfer model of analogue and mixed-signal front-end architectures for system-level design

Hierarchical multi-dimensional table lookup for model-compiler-based circuit simulation

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