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Computers, IEEE Transactions on

Issue 4 • Date April 2005

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Displaying Results 1 - 15 of 15
  • [Front cover]

    Page(s): c1
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  • [Inside front cover]

    Page(s): c2
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  • Antisequential suffix sorting for BWT-based data compression

    Page(s): 385 - 397
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    Suffix sorting requires ordering all suffixes of all symbols in an input sequence and has applications in running queries on large texts and in universal lossless data compression based on the Burrows Wheeler transform (BWT). We propose a new suffix lists data structure that leads to three fast, antisequential, and memory-efficient algorithms for suffix sorting. For a length-N input over a size-|X| alphabet, the worst-case complexities of these algorithms are Θ(N2), O(|X|N log(N/|X|)), and O(N√|X|log(N/|X|)), respectively. Furthermore, simulation results indicate performance that is competitive with other suffix sorting methods. In contrast, the suffix sorting methods that are fastest on standard test corpora have poor worst-case performance. Therefore, in comparison with other suffix sorting methods, suffix lists offer a useful trade off between practical performance and worst-case behavior. Another distinguishing feature of suffix lists is that these algorithms are simple; some of them can be implemented in VLSI. This could accelerate suffix sorting by at least an order of magnitude and enable high-speed BWT-based compression systems. View full abstract»

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  • Optimal lexicographic shaping of aggregate streaming data

    Page(s): 398 - 408
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    We investigate the problem of smoothing multiplexed network traffic when either a streaming server transmits data to multiple clients or a storage server accesses data from multiple storage devices or other servers. We introduce efficient algorithms for lexicographically optimally smoothing the aggregate bandwidth requirements over a shared network link. Possible applications include improvement in the bandwidth utilization of network links and reduction in the energy consumption of server hosts. In the data transmission problem, we consider the case in which the clients have different buffer capacities and unlimited bandwidth constraints or unlimited buffer capacities and different bandwidth constraints. For the data access problem, we handle the general case of a shared buffer capacity and individual network bandwidth constraints. Previous approaches for the data access problem handled either the case of only a single stream or did not compute the lexicographically optimal schedule. By provably minimizing the variance of the required aggregate bandwidth, lexicographically optimal smoothing makes the maximum resource requirements within the network more predictable and increases the useful resource utilization. It also improves fairness in sharing a network link among multiple users and makes new requests from future clients more likely to be successfully admitted without the need for rescheduling previously accepted traffic. With appropriate hardware and system support, data traffic smoothing can also reduce the energy consumption of the host processor and the communication links. Overall, we expect that efficient resource management at the network edges will better meet quality of service requirements without restricting the scalability of the system. View full abstract»

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  • Hierarchical adaptive dynamic power management

    Page(s): 409 - 420
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    Dynamic power management aims at extending battery life by switching devices to lower-power modes when there is a reduced demand for service. Static power management strategies can lead to poor performance or unnecessary power consumption when there are wide variations in the rate of requests for service. This paper presents a hierarchical scheme for adaptive dynamic power management (DPM) under nonstationary service requests. As the main theoretical contribution, we model the nonstationary request process as a Markov-modulated process with a collection of modes, each corresponding to a particular stationary request process. Optimal DPM policies are precalculated offline for selected modes using standard algorithms available for stationary Markov decision processes (MDPs). The power manager then switches online among these policies to accommodate the stochastic mode-switching request dynamics using an adaptive algorithm to determine the optimal switching rule based on the observed sample path. As a target application, we present simulations of hierarchical DPM for hard disk drives where the read/write request arrivals are modeled as a Markov-modulated Poisson process. Simulation results show that the power consumption of our approach under highly nonstationary request arrivals is less than that of a previously proposed heuristic approach and is even comparable to that of the optimal policy under stationary Poisson request process with the same arrival rate as the average arrival rate of the nonstationary request process. View full abstract»

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  • Tree parity machine rekeying architectures

    Page(s): 421 - 427
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    The necessity of securing the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e., small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronization of tree parity machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration, we evaluate characteristics of a standard-cell ASIC design realization as IP-core in 0.18μ-technology. View full abstract»

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  • Guidelines for scheduling some common computation-dags for Internet-based computing

    Page(s): 428 - 438
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    A "pebble game" is developed to model the process of scheduling computation-dags for Internet-based computing (IC, for short). Strategies are derived for scheduling three common, significant families of such dags for IC: reduction-meshes, which represent (the intertask dependencies of) computations that can be performed by "up-sweeps" of meshes; reduction-trees, which represent "accumulative" computations that can be performed by "up-sweeps" of trees; and FFT (fast fourier transform) dags, which represent a large variety of convolutional computations. Two criteria are used to assess the quality of a schedule: its memory requirements and its rate of producing tasks that are eligible for allocation to remote clients. These criteria are important because of, respectively, the typically enormous sizes of IC computations and the typical temporal unpredictability of remote clients in IC. In particular, a high production rate of eligible tasks decreases a computation's vulnerability to the gridlock that can occur when a computation stalls pending the return of intermediate results by remote clients. Under idealized assumptions, the schedules derived are optimal in the rate of producing eligible tasks and are either exactly or approximately optimal in memory requirements. View full abstract»

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  • Design and implementation of an SAN system based on the fiber channel protocol

    Page(s): 439 - 448
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    With the increasing demand for vast storage repositories, network storage has become important for mass data storage and processing, telescopic addressing and availability, and the quality of service and security of data storage. This situation demands the emergence of new technology in the data storage field. In this paper, TH-MSNS, a SAN system, is introduced. This system was designed and implemented based on the fiber channel protocol and its I/O route was tested. This paper introduces some of the key techniques in the network storage system, including an SCSI simulating target, intelligent and uniform storage management architecture, and the processing flow of the read/write commands. The software for the new storage area network system was implemented as a module in the kernel mode to improve its efficiency. The SCSI target adopts a layered design and standardized interface, which is compatible with various types of SCSI devices and can use different network protocols. The storage management software adopts distributed architecture, which enables higher interoperability and compatibility with various kinds of management protocols. TH-MSNS boasts characteristics such as high adaptability, high efficiency, high scalability, and high compatibility and is easy to maintain. View full abstract»

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  • Design and analysis of dual-rail circuits for security applications

    Page(s): 449 - 460
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    Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool. View full abstract»

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  • Software-based self-testing of embedded processors

    Page(s): 461 - 475
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1336 KB) |  | HTML iconHTML  

    Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations. View full abstract»

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  • Test vector embedding into accumulator-generated sequences: a linear-time solution

    Page(s): 476 - 484
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    The test set embedding problem is typically formed as follows: Given an n-stage pattern-generator and a test set, calculate the minimum number of steps that the generator needs to operate in order to generate all vectors in the test set. The cornerstone of a test set embedding technique is its embedding algorithm. An embedding algorithm, given an n-stage pattern generator initialized to a starting value and an n-bit target vector V, calculates the location of V in the generated sequence. In this paper, a novel algorithm is presented that calculates the location of a vector into a sequence generated by an n-stage accumulator accumulating a constant pattern. The time complexity of the algorithm is of the order O(n). To the best of our knowledge, this is the first embedding algorithm of the order O(n) that has been presented in the literature. Experiments performed on well-known benchmark circuits reveal that complete test sets are embedded in sequences of practically acceptable length. View full abstract»

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  • Fast bit-parallel GF(2n) multiplier for all trinomials

    Page(s): 485 - 490
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    Based on a new representation of GF(2n), we present two multipliers for all irreducible trinomials. Space complexities of the multipliers match the best results. The time complexity of one multiplier is TA + (1 + [log2 n])TX for all irreducible trinomials, where TA and TX are the delay of one 2-input AND and XOR gates, respectively. View full abstract»

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  • Efficient diminished-1 modulo 2n + 1 multipliers

    Page(s): 491 - 496
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB) |  | HTML iconHTML  

    In this work, we propose a new algorithm for designing diminished-1 modulo 2n+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations. View full abstract»

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  • TC Information for authors

    Page(s): c3
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    Freely Available from IEEE
  • [Back cover]

    Page(s): c4
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
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http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au