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Electron Devices, IEEE Transactions on

Issue 3 • Date March 2005

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  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Modeling and analysis of ZnSe-Ge HBTs

    Page(s): 299 - 304
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    A Gummel-Poon model is developed for ZnSe-Ge-GaAs heterojunction bipolar transistors (HBTs). In this structure, undoped Ge spacers are placed at the emitter-base and collector-base junctions. Injected current components as well as bulk, spacer, and space charge recombination current components are modeled. Early voltage and bandgap narrowing effects are included in the model. The device performance was simulated and compared with the experimental results. The paper shows a good agreement between our model and the experimental results. The paper shows also that using spacers would improve the device performance. The advantages of this model is that it is analytical, compact, and can be easily implemented in CAD tool programs to simulate single or double HBTs with similar or dissimilar materials structure for the emitter and collector. View full abstract»

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  • Hydrogen sensitivity of InP HEMTs with WSiN-based gate stack

    Page(s): 305 - 310
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    We have experimentally investigated the hydrogen sensitivity of InP high-electron mobility transistors (HEMTs) with a WSiN-Ti-Pt-Au gate stack. We have found that exposure to hydrogen produces a shift in the threshold voltage of these devices that is one order of magnitude smaller than published data on conventional Ti-Pt-Au gate HEMTs. We have studied this markedly improved reliability through a set of quasi-two-dimensional mechanical and electrostatic simulations. These showed that there are two main causes for the improvement of the hydrogen sensitivity. First, the separation of the Ti-layer from the semiconductor by a thick WSiN layer significantly reduces the stress in the heterostructure underneath the gate. Additionally, the relatively thinner heterostructure used in this study and the presence of an InP etch-stop layer with a small piezoelectric constant underneath the gate reduces the amount of threshold voltage shift that is caused by the mechanical stress. View full abstract»

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  • Velocity overshoot effects and scaling issues in III-V nitrides

    Page(s): 311 - 316
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    Empirical evidence from submicrometer technology in GaAs- and InGaAs-based field-effect transistors (FETs) has led to an expectation that velocities exceeding the steady state values would be observed in III-V nitride devices. However, scaling of devices down to 0.7 and 0.25 μm has so far not yielded any performance enhancement that may suggest an overshoot. In this paper, we examine transport in AlGaN-GaN heterojunction FETs (HFETs) to examine whether velocity overshoot effects occur. Our findings show that very high scattering rates when combined with unusual field profiles, result in a change in the local transport mechanism, and, in the source-gate region, combine to reduce/ify velocity overshoot effects. We also find that the effect of nonequilibrium phonons on transport in the channel is minimal, with the peak nonequilibrium phonon occupation being smaller than the equilibrium phonon occupation. View full abstract»

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  • SiGe HBTs on bonded SOI incorporating buried silicide layers

    Page(s): 317 - 324
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1296 KB) |  | HTML iconHTML  

    A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 μΩcm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000°C. Collector/base reverse diode tics show a voltage dependence of approximately V12/, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 × 1017 cm-3. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage. View full abstract»

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  • Effects of the parasitics on the time response of RCE-PDs

    Page(s): 325 - 334
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    Resonant cavity enhanced photodetectors (RCE-PDs) are promising candidates for applications in high-speed optical communications and interconnections. However, because parasitics effects of these high-speed photodetectors can significantly degrade the performance of the photodetector, then they must be carefully considered. Here, an accurate model for the time response of the RCE-PDs that includes the effects of their parasitics is presented. The effects of an inductor that may be added in series with the load resistor are also studied and it is shown that the external inductor can improve the performance of the photodetector because it compensates some of the degradations resulting from capacitive parasitics. The effects of the parasitics have been investigated for different dimensions of the photodetectors, different values of both the load resistance and the added inductor and also for different multiplication gains for the case of RCE-avalanche photodetectors. View full abstract»

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  • Analysis and circuit modeling of waveguide-separated absorption charge multiplication-avalanche photodetector (WG-SACM-APD)

    Page(s): 335 - 344
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    Waveguide photodetectors are considered leading candidates to overcome the bandwidth efficiency tradeoff of conventional photodetectors. In this paper, a theoretical physics-based model of the waveguide separated absorption charge multiplication avalanche photodetector (WG-SACM-APD) is presented. Both time and frequency modeling for this photodetector are developed and simulated results for different thicknesses of the absorption and multiplication layers and for different areas of the photodetector are presented. These simulations provide guidelines for the design of these high-performance photodiodes. In addition, a circuit model of the photodetector is presented in which the photodetector is a lumped circuit element so that circuit simulation of the entire photoreceiver is now feasible. The parasitics of the photodetector are included in the circuit model and it is shown how these parasitics degrade the photodetectors performance and how they can be partially compensated by an external inductor in series with the load resistor. The results obtained from the circuit model of the WG-SACM-APD are compared with published experimental results and good agreement is obtained. This circuit modeling can easily be applied to any WG-APD structure. The gain-bandwidth characteristic of WG-SACM-APD is studied for different areas and thicknesses of both the absorption and the multiplication layers. The dependence of the performance of the photodetector on the dimensions, the material parameters and the multiplication gain are also investigated. View full abstract»

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  • Binary addressing technique with duty cycle control for LCDs

    Page(s): 345 - 351
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    Introduction of duty cycle in the binary addressing technique is proposed to enable integration of liquid crystal display drivers with a digital system in a single chip. An analysis of this technique with duty-cycle control is presented. Effects of duty-cycle control on brightness uniformity of pixels in the liquid crystal display are discussed. A system on chip implementation of the technique is also demonstrated. View full abstract»

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  • Process and reliability of air-gap Cu interconnect using 90-nm node technology

    Page(s): 352 - 359
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2424 KB) |  | HTML iconHTML  

    A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant. View full abstract»

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  • Structural optimization of SUTBDG devices for low-power applications

    Page(s): 360 - 366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-κ gate dielectrics raise the off-state current (IOFF) due to the fringing field-induced barrier lowering effect. Suppressing the IOFF increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed IOFF, devices with less abrupt S/D-channel junctions suffer a drive current (ION) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in ION. The ION of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization. View full abstract»

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  • [110]-surface strained-SOI CMOS devices

    Page(s): 367 - 374
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB) |  | HTML iconHTML  

    We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS. View full abstract»

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  • Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

    Page(s): 375 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-π model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (Rbi), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (gm), dynamic base-emitter resistance (rπ), and base-emitter capacitance (Cπ) using the accurately extracted Rbi. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs. View full abstract»

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  • An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

    Page(s): 385 - 391
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted. View full abstract»

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  • Simulation of single-electron transport in nanostructured quantum dots

    Page(s): 392 - 396
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    Resonant tunneling via discrete energy states in single-electron electronic systems have been observed in many nanostructured configurations. The nodes of such circuits may assume either a continuum of energy states or a set of discrete states with different degeneracy factors. This paper presents a general-purpose simulator intended to provide a unique platform that is able to simulate such circuits. The model is described and then used to study some typical simple circuits. It is shown that even for simple circuits, the interplay between energy spectrum, sensitivity to voltage variations and Coulomb blockade conditions might lead to very complicated current-voltage characteristics. View full abstract»

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  • Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

    Page(s): 397 - 405
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB) |  | HTML iconHTML  

    In this paper, we show the benefits of using asymmetric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% reduction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates. View full abstract»

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  • Detailed investigation of geometrical factor for pseudo-MOS transistor technique

    Page(s): 406 - 412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility. View full abstract»

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  • Effect of doped substrate on GaAs-AlGaAs interfacial workfunction IR detector response through cavity effect

    Page(s): 413 - 418
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    In this paper, results are reported showing response enhancement in GaAs-AlGaAs IR detectors using a doped substrate to increase reflection, enhancing the resonant cavity effect. Responsivity for heterojunction interfacial workfunction detectors grown on semi-insulating (SI) and doped substrates are compared. For a device grown on an SI substrate, a 9-μm resonance peak had a response of 1.5 mA/W while a similar device on an n-doped substrate showed 12 mA/W. Also, the difference between response under forward and reverse bias (3 versus 12 mA/W) for the sample grown on the doped substrate, as well as calculated results confirm that the increased response is due to the resonant enhancement. An optimized design for a 15-μm peak (24 μm 0 response threshold) detector grown on a doped substrate could expect a peak response of 4 A/W with a 50% quantum efficiency and D* ∼ 2 × 1010 Jones at the background limited temperature of 50 K. View full abstract»

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  • Silicon-based micro-Fourier spectrometer

    Page(s): 419 - 426
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A novel Fourier spectrometer based on a partly transparent thin-film detector in combination with a tunable silicon micromachined mirror was developed. The operation principle based on the detection of an intensity profile of a standing-wave by introducing a partly transparent detector in the standing-wave. Varying the position of the mirror results in a phase shift of the standing-wave and thus in a change of the optical intensity profile within the detector. The photoelectric active region of the sensor is thinner than the wavelength of the incoming light, so that the modulation of the intensity leads to the modulation of the photocurrent. The spectral information of the incoming light can be determined by the Fourier transform of the sensor signal. Based on the linear arrangement of the sensor and the mirror, the spectrometer facilitates the realization of one- and two-dimensional arrays of spectrometers combining spectral and spatial resolution. The operation principle of the spectrometer will be described and the influence of the detector design on the spectrometer performance will be discussed. A spectral resolution of down to 6 nm was achieved under real-time imaging conditions. View full abstract»

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  • NAND-type DRAM-on-SGT

    Page(s): 427 - 429
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    In this brief, we propose a novel NAND-type DRAM-on-surrounding-gate transistor (SGT) architecture for high-density and low-voltage memory. The cell structure is composed of NAND-type DRAM vertically stacked on an SGT and an SGT-type capacitor. A cell size of 4F2 can be achieved. Since it operates as a gain cell, it is possible to obtain a sufficient amount of signal charge. The device was fabricated with a 0.8-μm lithography system. View full abstract»

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  • Improving the activation of the P+ region of low-temperature polycrystalline Si TFTs by using solid-phase Crystallization

    Page(s): 429 - 432
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    We have developed a low-temperature fabrication process for making thin-film transistors (TFTs) with highly activated source and drain regions by utilizing pre-amorphization by Ge-ion implantation followed by solid-phase crystallization. The sheet resistances of the p+ polysilicon layers formed by B-ion implantation with and without Ge-ion implantation were, respectively, 200 and 1500 Ω/sq. We confirmed reducing the sheet resistance of p+ polysilicon increases the on-current of TFTs on glass substrates. This process is promising for making high-performance CMOS peripheral circuits for liquid crystal display panels. View full abstract»

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  • Effect of induced gate noise at zero drain bias in field-effect transistors

    Page(s): 432 - 434
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    According to classical theories, a MOS transistor with zero source-to-drain voltage behaves like a passive resistor exhibiting channel thermal noise and the effect of induced gate noise vanishes. Here, we show that the effect of induced gate noise persists as conductance fluctuations even under these "equilibrium" conditions without disturbing the Nyquist relationship governing the channel thermal noise. View full abstract»

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  • Special issue on non-classical Si CMOS devices and technologies: Extending the roadmap

    Page(s): 435
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  • ESSDERC ESSCIRC 2005

    Page(s): 436
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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology