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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • March 2005

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  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2005, Page(s): c2
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  • A fast pseudo-Boolean constraint solver

    Publication Year: 2005, Page(s):305 - 317
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB) | HTML iconHTML

    Linear pseudo-Boolean (LPB) constraints denote inequalities between arithmetic sums of weighted Boolean functions and provide a significant extension of the modeling power of purely propositional constraints. They can be used to compactly describe many discrete electronic design automation problems with constraints on linearly combined, weighted Boolean variables, yet also offer efficient search s... View full abstract»

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  • Predicated switching - optimizing speculation on EPIC machines

    Publication Year: 2005, Page(s):318 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB) | HTML iconHTML

    Explicitly parallel instruction computing (EPIC) processors are a very attractive platform for many of today's multimedia and communications applications. In particular, clustered EPIC machines can take aggressive advantage of the available instruction-level parallelism, while maintaining high energy-delay efficiency. However, multicluster machines are more challenging to compile to than centraliz... View full abstract»

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  • Interconnect-aware low-power high-level synthesis

    Publication Year: 2005, Page(s):336 - 351
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB) | HTML iconHTML

    Interconnects (wires, buffers, clock distribution networks, multiplexers, and busses) consume a significant fraction of total circuit power. In this paper, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. It not only reduces datapath unit power co... View full abstract»

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  • MOS table models for circuit simulation

    Publication Year: 2005, Page(s):352 - 362
    Cited by:  Papers (10)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    Compact MOSFET models for circuit simulation face several competing requirements, such as fast execution times, good accuracy and small memory requirements. This paper describes novel interpolation methods for accurate evaluation of MOSFET characteristics in weak, moderate, and strong inversion regions. These methods form the basis of a new table look-up model implemented in SPICE3F5. The table mo... View full abstract»

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  • Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

    Publication Year: 2005, Page(s):363 - 381
    Cited by:  Papers (41)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1256 KB) | HTML iconHTML

    Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit. In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been deve... View full abstract»

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  • MARS-a multilevel full-chip gridless routing system

    Publication Year: 2005, Page(s):382 - 394
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (890 KB) | HTML iconHTML

    This paper presents MARS, a novel multilevel full-chip gridless routing system. The multilevel framework with recursive coarsening and refinement allows for scaling of our gridless routing system to very large designs. The downward pass of recursive coarsening builds the representations of routing regions at different levels while the upward pass of iterative refinement allows a gradually improved... View full abstract»

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  • Timing-driven partitioning-based placement for island style FPGAs

    Publication Year: 2005, Page(s):395 - 406
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB) | HTML iconHTML

    In traditional field programmable gate array (FPGA) placement methods, there is virtually no coupling between placement and routing. Performing simultaneous placement and detailed routing has been shown to generate much better placement qualities, but at the expense of significant runtime penalties (Nag and Rutenbar, 1998). We propose a routing-aware partitioning-based placement algorithm for FPGA... View full abstract»

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  • On-chip power-supply network optimization using multigrid-based technique

    Publication Year: 2005, Page(s):407 - 417
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (385 KB) | HTML iconHTML

    In this paper, we present a novel multigrid-based technique for the problem of on-chip power-supply network optimization. The multigrid-based technique is applied to reduce a large-scale network to a much coarser one. The reduced network can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. Due to the adoption of an accurate resi... View full abstract»

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  • A general hierarchical circuit modeling and simulation algorithm

    Publication Year: 2005, Page(s):418 - 434
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced circuit matrix and compute the circuit characteristics in rational function forms for very large linear... View full abstract»

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  • Test planning for modular testing of hierarchical SOCs

    Publication Year: 2005, Page(s):435 - 448
    Cited by:  Papers (23)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchica... View full abstract»

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  • Built-in sequential fault self-testing of array multipliers

    Publication Year: 2005, Page(s):449 - 460
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB) | HTML iconHTML

    Microprocessor datapath architectures operate on signed numbers usually represented in two's-complement or sign-magnitude formats. The multiplication operation is performed by optimized array multipliers of various architectures which are often produced by automatic module generators. Array multipliers have either a standard, nonrecoded signed (or unsigned) architecture or a recoded (modified Boot... View full abstract»

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  • Optimum positioning of interleaved repeaters in bidirectional buses

    Publication Year: 2005, Page(s):461 - 469
    Cited by:  Papers (12)  |  Patents (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    It is shown in this paper that the optimum position of interleaved repeaters for minimum delay and noise is not the midpoint as commonly practiced. A closed-form solution for the optimum position has been derived in this paper and verified by simulation. Bidirectional buses with the optimum interleaved repeater position are compared to commonly used bidirectional buses and shown to provide an impr... View full abstract»

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  • Intrabus crosstalk estimation using word-level statistics

    Publication Year: 2005, Page(s):469 - 478
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    We propose two word-level statistical techniques to estimate the probability of crosstalk events on the signal lines of a system bus. Given the word-level statistical parameters, namely mean, standard deviation, and lag-one temporal correlation coefficient, we analytically estimate the bit-level crosstalk probability. To linearize the complexity and efficiently scale the estimation technique for l... View full abstract»

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  • Capacitive coupling noise in high-speed VLSI circuits

    Publication Year: 2005, Page(s):478 - 488
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB) | HTML iconHTML

    Rapid technology scaling along with the continuous increase in the operation frequency cause the crosstalk noise to become a major source of performance degradation in high-speed integrated circuits. This paper presents an efficient metric to estimate the capacitive crosstalk in nanometer high-speed very large scale integration circuits. In particular, we provide closed-form expressions for the pe... View full abstract»

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  • On-chip embedding mechanisms for large sets of vectors for delay test

    Publication Year: 2005, Page(s):488 - 497
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    On-chip embedding of deterministic patterns is used for built-in test-pattern generation of large sets of vector pairs for path delay fault testing. A hardware efficient two-phase synthesis procedure is proposed to synthesize the test-pattern generator. Acceptable test-cycle requirements are met using a recent method, which reduces the test embedding problem to that of embedding the first vector i... View full abstract»

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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 498
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  • IEEE order form for reprints

    Publication Year: 2005, Page(s): 499
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  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2005, Page(s): 500
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu