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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 2 • Date Feb. 2005

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2005 , Page(s): c1 - c4
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  • IEEE Transactions on Circuits and Systems–I: Regular Papers publication information

    Publication Year: 2005 , Page(s): c2
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  • A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices

    Publication Year: 2005 , Page(s): 253 - 261
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB) |  | HTML iconHTML  

    We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-μm silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates. View full abstract»

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  • Precise, wide-range approximations to arc sine function suitable for analog implementation in sensors and instrumentation applications

    Publication Year: 2005 , Page(s): 262 - 270
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB) |  | HTML iconHTML  

    This paper presents four newly developed algebraic approximations of the inverse sine function, defined for the full [-1,+1] input range. These approximations contain few terms, and have numerical coefficients with low number of significant figures. The maximum absolute errors of the formulas range between 4.07×10-4% and 5.64×10-2% of the maximum value (i.e., π/2) returned by the arc sine function. These approximations are particularly suited to the determination of mechanical and electrical angles in sensors and instrumentation applications. One of the proposed expressions has been implemented using analog electronic circuitry. The converter built was successfully tested and characterized using both a PC-based test rig, and a commercial resolver. The theory, computer simulation and some experimental results are given. View full abstract»

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  • A rail-to-rail amplifier input stage with ±0.35%gm fluctuation

    Publication Year: 2005 , Page(s): 271 - 282
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1384 KB) |  | HTML iconHTML  

    A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant gm is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-μm process. The resulting differential pair had a constant transconductance that varied by only ±0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of ±1.5V, resulting in only ±1% fluctuation in gm for input common modes from -2 to 2 V. View full abstract»

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  • A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range

    Publication Year: 2005 , Page(s): 283 - 291
    Cited by:  Papers (19)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-μm CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption. View full abstract»

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  • A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

    Publication Year: 2005 , Page(s): 292 - 304
    Cited by:  Papers (18)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB) |  | HTML iconHTML  

    A charge-domain quadrature sampling circuit realization in 0.35 μm CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply. View full abstract»

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  • Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors

    Publication Year: 2005 , Page(s): 305 - 317
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    In this paper, a biasing technique for cancelling second-order intermodulation (IM2) distortion and enhancing second-order intercept point (IIP2) in common-source and common-emitter RF transconductors is presented. The proposed circuit can be utilized as an RF input transconductor in double-balanced downconversion mixers. By applying the presented technique, the achievable IIP2 of the mixer is limited by the linearity of the switching devices, component mismatches, and offsets. The proposed circuit has properties similar to the conventional differential pair transconductor in that it ideally displays no IM2 distortion. However, the presented circuit is more suitable for operation at low supply voltages because it has only one device stacked between the transconductor input and output. In the conventional differential pair, two devices consume the voltage headroom. The noise performance of the proposed transconductor is similar to the noise performance of the traditional common-source (emitter) and differential pair transconductors at given bias and device dimensions. On the other hand, the third-order intercept point (IIP3) of the presented transconductor is slightly higher than the IIP3 of the differential pair transconductor at given bias. Finally, the proposed circuit can also be employed as a current mirror, the ratio of which is very insensitive to the voltage swings at the gate or base of the current mirrored transistor. View full abstract»

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  • Well-behaved global on-chip interconnect

    Publication Year: 2005 , Page(s): 318 - 323
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes. View full abstract»

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  • High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

    Publication Year: 2005 , Page(s): 324 - 337
    Cited by:  Papers (38)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches. View full abstract»

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  • Trigonometric polynomial interpolation for timing recovery

    Publication Year: 2005 , Page(s): 338 - 349
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1208 KB) |  | HTML iconHTML  

    In an all-digital timing-adjustment system for digital modems, interpolation can be employed to recover samples that are synchronous with the data symbols. In this paper, a novel interpolation method is described for such systems. Instead of approximating a continuous-time signal with a conventional (algebraic) polynomial and computing the synchronized samples using a Farrow structure, a trigonometric polynomial is employed. It is demonstrated that this approach produces a particularly simple implementation structure, reduces computational delay and, for practical signals, can improve the interpolation performance. Moreover, to recover a synchronized sample from existing samples, given a timing offset, it is shown that the method can be optimized such that a recovered sample's interpolation error is minimized for that specific timing offset value. The input signal's spectrum is also taken into account. Simulation results indicate that the method can achieve the best performance among all state-of-the-art methods tested. In addition, the optimal interpolator can be implemented without increased hardware requirements. View full abstract»

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  • FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

    Publication Year: 2005 , Page(s): 350 - 365
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware. View full abstract»

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  • Feedback control of limit cycles: a switching control strategy based on nonsmooth bifurcation theory

    Publication Year: 2005 , Page(s): 366 - 378
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    In this paper, we present a method to control limit cycles in smooth planar systems making use of the theory of nonsmooth bifurcations. By designing an appropriate switching controller, the occurrence of a corner-collision bifurcation is induced on the system and the amplitude and stability properties of the target limit cycle are controlled. The technique is illustrated through a representative example. View full abstract»

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  • Enhanced phase noise modeling of fractional-N frequency synthesizers

    Publication Year: 2005 , Page(s): 379 - 395
    Cited by:  Papers (37)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB) |  | HTML iconHTML  

    Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage control oscillator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of ΔΣ sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations. View full abstract»

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  • Geometric modeling of nonlinear RLC circuits

    Publication Year: 2005 , Page(s): 396 - 404
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    In this paper, the dynamics of nonlinear RLC circuits including independent and controlled voltage or current sources is described using the Brayton-Moser equations. The underlying geometric structure is highlighted and it is shown that the Brayton-Moser equations can be written as a dynamical system with respect to a noncanonical Dirac structure. The state variables are inductor currents and capacitor voltages. The formalism can be extended to include circuits with elements in excess, as well as general noncomplete circuits. Relations with the Hamiltonian formulation of nonlinear electrical circuits are clearly pointed out. View full abstract»

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  • A new method for the reduction of crosstalk and echo in multiconductor interconnections

    Publication Year: 2005 , Page(s): 405 - 416
    Cited by:  Papers (23)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    Crosstalk and echo can be reduced in multiconductor interconnections, using (truly) matched terminations and a different modal variable for each transmission channel. We first study a conventional technique for reducing reflections, using grounded linear two-terminal circuit elements. Using the concepts of modal voltages and modal currents, we define a new method for the reduction of crosstalk and echo, which involves specific terminations, specific transmitting circuits to send signals, and specific receiving circuits to receive signals. We establish the design equations and show that the new method is related to a particular choice of eigenvectors, called associated eigenvectors. Simulations of two examples of implementation of this method confirm that it provides reduced crosstalk and echo. We also discuss the implementation of the new method with an interconnection having identical propagation constants for all modes. Finally, we compare the new method with a different concept based on modal variables and unspecified terminations. View full abstract»

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  • Global asymptotic and robust stability of recurrent neural networks with time delays

    Publication Year: 2005 , Page(s): 417 - 426
    Cited by:  Papers (175)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    In this paper, two related problems, global asymptotic stability (GAS) and global robust stability (GRS) of neural networks with time delays, are studied. First, GAS of delayed neural networks is discussed based on Lyapunov method and linear matrix inequality. New criteria are given to ascertain the GAS of delayed neural networks. In the designs and applications of neural networks, it is necessary to consider the deviation effects of bounded perturbations of network parameters. In this case, a delayed neural network must be formulated as a interval neural network model. Several sufficient conditions are derived for the existence, uniqueness, and GRS of equilibria for interval neural networks with time delays by use of a new Lyapunov function and matrix inequality. These results are less restrictive than those given in the earlier references. View full abstract»

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  • Nonparametric identification of nonlinearities in block-oriented systems by orthogonal wavelets with compact support

    Publication Year: 2005 , Page(s): 427 - 442
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    The paper addresses the problem of identification of nonlinear characteristics in a certain class of discrete-time block-oriented systems. The systems are driven by random stationary white processes (independent and identically distributed input sequences) and disturbed by stationary, white, or colored random noise. The prior information about nonlinear characteristics is nonparametric. In order to construct identification algorithms, the orthogonal wavelets of compact support are applied, and a class of wavelet-based models is introduced and examined. It is shown that under moderate assumptions, the proposed models converge almost everywhere (in probability) to the identified nonlinear characteristics, irrespective of the noise model. The rule for optimum model-size selection is given and the asymptotic rate of convergence of the model error is established. It is demonstrated that, in some circumstances, the wavelet models are, in particular, superior to classical trigonometric and Hermite orthogonal series models worked out earlier. View full abstract»

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  • Cryptographically secure substitutions based on the approximation of mixing maps

    Publication Year: 2005 , Page(s): 443 - 453
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    In this paper, we explore, following Shannon's suggestion that diffusion should be one of the ingredients of resistant block ciphers, the feasibility of designing cryptographically secure substitutions (think of S-boxes, say) via approximation of mixing maps by periodic transformations. The expectation behind this approach is, of course, that the nice diffusion properties of such maps will be inherited by their approximations, at least if the convergence rate is appropriate and the associated partitions are sufficiently fine. Our results show that this is indeed the case and that, in principle, block ciphers with close-to-optimal immunity to linear and differential cryptanalysis (as measured by the linear and differential approximation probabilities) can be designed along these guidelines. We provide also practical examples and numerical evidence for this approximation philosophy. View full abstract»

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  • Design of binary sequences with tunable exponential autocorrelations and run statistics based on one-dimensional chaotic maps

    Publication Year: 2005 , Page(s): 454 - 462
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    This paper describes simple design methods of chaotic binary sequences with prescribed exponential autocorrelation properties and run statistics. We employ one-dimensional piecewise monotonic onto maps and a simple threshold function for generating such sequences. Some examples of such designs are also given. Furthermore, bounds on run statistics are discussed and compared to the result for sequences of general binary random variables. View full abstract»

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  • The Fourth International Workshop on Multidimensional (nD) Systems NDS 2005

    Publication Year: 2005 , Page(s): 463
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    Freely Available from IEEE
  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005 , Page(s): 464
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2005 , Page(s): c3
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras