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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 2 • Date Feb. 2005

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • Design of wireless on-wafer submicron characterization system

    Publication Year: 2005, Page(s):169 - 180
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (662 KB) | HTML iconHTML

    A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no process or design changes are required. Most compelling is that wafer contact is not required, thereby enabling the in-line process control/monitoring of... View full abstract»

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  • A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

    Publication Year: 2005, Page(s):181 - 190
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (843 KB) | HTML iconHTML

    In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpol... View full abstract»

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  • A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

    Publication Year: 2005, Page(s):191 - 200
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1747 KB) | HTML iconHTML

    A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data r... View full abstract»

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  • A "Flying-Adder" frequency synthesis architecture of reducing VCO stages

    Publication Year: 2005, Page(s):201 - 210
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (685 KB) | HTML iconHTML

    The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a voltage-controlled oscillator (VCO) of multiple delay stages. Since the invention of this architecture, various improvements have been made during many implementations of this technique. One of the remaining issues is to reduce the number of delay stages inside the VCO for the benefit of low power consu... View full abstract»

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  • Energy-aware wireless systems with adaptive power-fidelity tradeoffs

    Publication Year: 2005, Page(s):211 - 225
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1617 KB) | HTML iconHTML

    Wireless networked embedded systems, such as multimedia terminals, sensor nodes, etc., present a rich domain for making energy/performance/quality tradeoffs based on application needs, network conditions, etc. Energy awareness in these systems is the ability to perform tradeoffs between available battery energy and application quality requirements. In this paper, we show how operating system direc... View full abstract»

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  • Static task-scheduling algorithms for battery-powered DVS systems

    Publication Year: 2005, Page(s):226 - 237
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB) | HTML iconHTML

    Battery lifetime enhancement is a critical design parameter for mobile computing devices. Maximizing the battery lifetime is a particularly difficult problem due to the nonlinearity of the battery behavior and its dependence on the characteristics of the discharge profile. In this paper, we address the problem of task scheduling with voltage scaling in a battery-powered single and multiprocessor s... View full abstract»

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  • Efficient algorithms for multilevel power estimation of VLSI circuits

    Publication Year: 2005, Page(s):238 - 254
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB) | HTML iconHTML

    This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SP... View full abstract»

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  • A micropower low-voltage multiplier with reduced spurious switching

    Publication Year: 2005, Page(s):255 - 265
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (785 KB) | HTML iconHTML

    We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken ... View full abstract»

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  • Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder

    Publication Year: 2005, Page(s):266 - 277
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (403 KB) | HTML iconHTML

    This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates that in every case a generic rounding architecture based on a prefix adder with a small amount of addit... View full abstract»

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  • A transaction-based unified architecture for simulation and emulation

    Publication Year: 2005, Page(s):278 - 287
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This pape... View full abstract»

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  • TCG: A transitive closure graph-based representation for general floorplans

    Publication Year: 2005, Page(s):288 - 292
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    In this brief, we introduce the concept of the P*-admissible representation and propose a P*-admissible, transitive closure graph-based representation for general floorplans, called transitive closure graph (TCG), and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, ... View full abstract»

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  • International Symposium on Low Power Electronics and Design (ISLPED'05)

    Publication Year: 2005, Page(s): 293
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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 294
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  • Celebrating the vitality of technology the Proceedings of the IEEE [advertisement]

    Publication Year: 2005, Page(s): 295
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  • Explore IEL IEEE's most comprehensive resource

    Publication Year: 2005, Page(s): 296
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu