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IEE Review

Issue 1 • Date 17 Jan 1991

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Displaying Results 1 - 4 of 4
  • Taming Leo-overcoming the inherent unreliability of Leo I

    Page(s): 13 - 17
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    Leo I was a unique machine using thermionic valves based on the Cambridge Edsac Mark I. It was built between 1949 and 1953 as a simple payroll computer. The author looks at the dependability, sources of unreliability and operational practices of the Leo I computer View full abstract»

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  • Tropical trains-the Calcutta Metro

    Page(s): 19 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    In Calcutta, India, the traffic problems were so bad that there was no alternative but to build an underground rapid mass-transport system; construction of the Calcutta Metro began in the mid 1980s. The author discusses the construction, ventilation, traction, signalling, human factors, safety and routing of the new metro View full abstract»

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  • All light now-fibre amplifiers and their impact on telecoms

    Page(s): 35 - 39
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A large proportion of the UK trunk communications for data and telephony needs are now met by single-mode optical fibre cable systems. Network planners need to increase the capacity of optical systems but this is becoming increasingly difficult. The preferred way to increase the distance over which an optical cable can operate is to place optical amplifiers in the line. The author looks at how optical amplifiers can be improved to make this idea feasible View full abstract»

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  • Testing time for ASICs

    Page(s): 27 - 31
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    Application specific integrated circuits (ASICs) have been one of the electronics success stories of the 1980s. The rise in their complexity means that chips are now so complex that it is no longer feasible for a test engineer to understand the design at the level of detail required to generate a test program. ASIC designers are increasingly assuming responsibility for test program development. Fault simulation is discussed and automatic test-vector generation and on-chip test circuits are reviewed View full abstract»

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