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Circuits and Devices Magazine, IEEE

Issue 1 • Date Jan.-Feb. 2005

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Displaying Results 1 - 15 of 15
  • Advertisers Index

    Page(s): 40
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  • The power of functional scaling: beyond the power consumption challenge and the scaling roadmap

    Page(s): 27 - 35
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    The relentless progress of silicon technology in the last few decades has been astounding, owing to device scaling. The characteristic lengths associated with successive generations of the technology have decreased, producing higher performance devices and circuits. At various times, people have predicted the end of scaling because of apparent barriers, but these barriers have fallen thanks to the ingenuity of the scientists and engineers involved in the technology. This has occurred through developments and changes in device design, the introduction of new materials, improved processing technologies and tools - both engineering and simulation - and other innovative approaches. The resulting increases in the densities of devices and their functionality in circuits now make the issue of power dissipation, both static and dynamic, a serious constraint to future scaling advances. In this article, a new very large scale integration (VLSI) structure is proposed and demonstrated to address these issues, using the 3D integration of high performance Ge-on-insulator (GOI) field effect transistors above conventional interconnects and Si devices. View full abstract»

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  • VLSI Designer's interface

    Page(s): 3 - 37
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  • The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

    Page(s): 16 - 26
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    The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node. This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS. This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures. This paper provides a brief introduction to each of the new nonclassical CMOS structures. This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS. A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided. View full abstract»

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  • Electronic and Optoelectronic Properties of Semiconductor Structures [Book Review]

    Page(s): 37
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  • A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions

    Page(s): 4 - 15
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    The IC industry has been rapidly and consistently scaling the design rules, increasing the chip and wafer size, and cleverly improving the design of devices and circuits for over 35 years. As a result, the industry has enjoyed exponential increases in chip speed and functional density versus time combined with exponential decreases in power dissipation and cost per function versus time, as projected by Moore's Law by G.E. Moore (1995). As metal-oxide semiconductor field-effect transistors (MOSFETs) are scaled to deep submicron dimensions, the integrated circuit (IC) industry is running into increasing difficulties in continuing to scale at the accustomed rate, owing to the small dimensions and certain key device, material, and process limits that are being approached. View full abstract»

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  • Frequency Selective Surfaces: Theory and Design [Book Review]

    Page(s): 36
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    Freely Available from IEEE
  • Integrated Passive Component Technology [Book Review]

    Page(s): 36
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    Freely Available from IEEE
  • IEEE Circuits & Devices

    Page(s): 0_1
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    Freely Available from IEEE
  • IEEE Circuits & Devices Magazine

    Page(s): 0_2
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    Freely Available from IEEE
  • IEEE Circuits & Devices - Table of contents

    Page(s): 1
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    Freely Available from IEEE
  • Conference calendar

    Page(s): 38 - 39
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  • Brain teaser challenge

    Page(s): 0_3
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  • Embedded Systems Conference - San Francisco - Mar. 6-10, 2005

    Page(s): 0_4
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    Freely Available from IEEE

Aims & Scope

IEEE Circuits and Devices Magazine (1985-2006) covers the design, implementation, packaging, and manufacture of micro-electronic and photonic devices, circuits and systems

 

This Magazine ceased publication in 2006.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dr. Ronald W. Waynant
r.waynant@ieee.org