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IEEE Transactions on Computers

Issue 3 • March 2005

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • Guest Editors' Introduction: Special Issue on Computer Arithmetic

    Publication Year: 2005, Page(s):241 - 242
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  • Addition related arithmetic operations via controlled transport of charge

    Publication Year: 2005, Page(s):243 - 256
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    This work investigates the single electron tunneling (SET) technology-based computation of basic addition related arithmetic functions, e.g., addition and multiplication, via a novel computation paradigm, which we refer to as electron counting arithmetic, that is based on controlling the transport of discrete quantities of electrons within the SET circuit. First, assuming that the number of contro... View full abstract»

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  • Efficient techniques for binary-to-multidigit multidimensional logarithmic number system conversion using range-addressable look-up tables

    Publication Year: 2005, Page(s):257 - 271
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2472 KB) | HTML iconHTML

    The multidimensional logarithmic number system (MDLNS), which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and has the ability to use multiple MDLNS components, or digits. Unlike the LNS, there is no monotonic relationship between standard binary representations and MDLNS re... View full abstract»

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  • High-performance low-power left-to-right array multiplier design

    Publication Year: 2005, Page(s):272 - 283
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1984 KB) | HTML iconHTML

    We present a high-performance low-power design of linear array multipliers based on a combination of the following techniques: signal flow optimization in [3:2] adder array for partial product reduction, left-to-right leapfrog (LRLF) signal flow, and splitting of the reduction array into upper/lower parts. The resulting upper/lower LRLF (ULLRLF) multiplier is compared with tree multipliers. From a... View full abstract»

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  • Architecture and implementation of a vector/SIMD multiply-accumulate unit

    Publication Year: 2005, Page(s):284 - 293
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB) | HTML iconHTML

    This work presents 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64×64, two 32×32, four 16×16, or eight 8×8 bit signed/unsigned multiply using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized" b... View full abstract»

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  • Digit selection for SRT division and square root

    Publication Year: 2005, Page(s):294 - 303
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a redundant representation. The number of leading bits needed depends on the quotient radix and digit set, and is usually found by an extensive search, to assure that the next quotient digit can be chosen as valid for all poi... View full abstract»

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  • High-speed function approximation using a minimax quadratic interpolator

    Publication Year: 2005, Page(s):304 - 318
    Cited by:  Papers (75)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1384 KB) | HTML iconHTML

    A table-based method for high-speed function approximation in single-precision floating-point format is presented in this paper. Our focus is the approximation of reciprocal, square root, square root reciprocal, exponentials, logarithms, trigonometric functions, powering (with a fixed exponent p), or special functions. The algorithm presented here combines table look-up, an enhanced minimax quadra... View full abstract»

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  • Multipartite table methods

    Publication Year: 2005, Page(s):319 - 330
    Cited by:  Papers (86)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB) | HTML iconHTML

    A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite... View full abstract»

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  • A new range-reduction algorithm

    Publication Year: 2005, Page(s):331 - 339
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    Range-reduction is a key point for getting accurate elementary function routines. We introduce a new algorithm that is fast for input arguments belonging to the most common domains, yet accurate over the full double-precision range. View full abstract»

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  • Searching worst cases of a one-variable function using lattice reduction

    Publication Year: 2005, Page(s):340 - 346
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    We propose a new algorithm to find worst cases for the correct rounding of a mathematical function of one variable. We first reduce this problem to the real small value problem - i.e., for polynomials with real coefficients. Then, we show that this second problem can be solved efficiently by extending Coppersmith's work on the integer small value problem - for polynomials with integer coefficients... View full abstract»

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  • High-throughput CORDIC-based geometry operations for 3D computer graphics

    Publication Year: 2005, Page(s):347 - 361
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1488 KB) | HTML iconHTML

    Graphics processors require strong arithmetic support to perform computational kernels over data streams. Because of the current implementation using the basic arithmetic operations, the algorithms are given in algebraic terms. However, since the operations are really of a geometric nature, it seems to us that more flexibility in the implementation is obtained if the description is given in a high... View full abstract»

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  • Five, six, and seven-term Karatsuba-like formulae

    Publication Year: 2005, Page(s):362 - 369
    Cited by:  Papers (63)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    The Karatsuba-Ofman algorithm starts with a way to multiply two 2-term (i.e., linear) polynomials using three scalar multiplications. There is also a way to multiply two 3-term (i.e., quadratic) polynomials using six scalar multiplications. These are used within recursive constructions to multiply two higher-degree polynomials in subquadratic time. We present division-free formulae, which multiply... View full abstract»

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  • A class of unidirectional bit serial systolic architectures for multiplicative inversion and division over GF(2m)

    Publication Year: 2005, Page(s):370 - 380
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB) | HTML iconHTML

    A class of universal unidirectional bit serial systolic architectures for multiplicative inversion and division over Galois field GF(2m) is presented. The field elements are represented with polynomial (standard) basis. These systolic architectures have no carry propagation structures and are suitable for hardware implementations where the dimension of the field is large and may vary. T... View full abstract»

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  • Call For Papers

    Publication Year: 2005, Page(s): 381
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  • [Advertisement]

    Publication Year: 2005, Page(s): 382
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  • [Advertisement]

    Publication Year: 2005, Page(s): 383
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  • [Advertisement]

    Publication Year: 2005, Page(s): 384
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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org