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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb. 2005

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Displaying Results 1 - 25 of 27
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Changes to the Editorial Board

    Page(s): 145
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  • Characteristics of InxAl1-xN-GaN high-electron mobility field-effect transistor

    Page(s): 146 - 150
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    GaN-based field effect transistors commonly include an AlxGa1-xN barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the AlxGa1-xN-GaN heterostructure can be, in principle, avoided by the use of InxAl1-xN as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an InxAl1-x-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In0.04Al0.96N-GaN heterostructure reach 4×1013 cm-2 at room temperature, and Hall mobility is 480 and 750 cm2/V · s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and InxAl1-xN. Devices with a gate length of 0.7 μm exhibit ft and fmax values of 13 and 11 GHz, respectively. View full abstract»

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  • n+-InAs-InAlAs recess gate technology for InAs-channel millimeter-wave HFETs

    Page(s): 151 - 158
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    We report a submicrometer, self-aligned recess gate technology for millimeter-wave InAs-channel heterostructure field effect transistors. The recess gate structure is obtained in an n+-InAs-InAlAs double cap layer structure with a citric-acid-based etchant. From molecular-beam epitaxy-grown material functional devices with 1000-, 500-, and 200-nm gate length were fabricated. From all three device geometries we obtain drive currents of at least 500 mA/mm, gate leakage currents below 2 mA/mm, and RF-transconductance of 1 S/mm. For the 200-nm gate length device fτ and fmax are 162 and 137 GHz, respectively. For the 500-nm gate length device fτ and fmax are 89 and 140 GHz, respectively. We observe scaling limitations at 200-nm gate length, in particular a negative threshold voltage shift from -550 to -810 mV, increased kink-effect, and a high gate-to-drain capacitance of 0.5 pF/mm. The present limitations to device scaling are discussed. View full abstract»

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  • Influence of surface defect charge at AlGaN-GaN-HEMT upon Schottky gate leakage current and breakdown voltage

    Page(s): 159 - 164
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    The relation between Schottky gate leakage current and the breakdown voltage of AlGaN-GaN high-electron mobility transistors (HEMTs) is discussed based on the newly introduced simple, yet useful, surface defect charge model. This model represents the leakage current caused by the positive charge in the surface portion of AlGaN layer induced by process damage such as nitrogen vacancies. The new model has been implemented into a two-dimensional device simulator, and the relationship between the gate leakage current and the breakdown voltage was simulated. The simulation results reproduced the relationship obtained experimentally between the leakage current and the breakdown voltage. Further simulation and experiment results show that the breakdown voltage is maintained even if the defect charge exists up to the defect charge density of 2.5×1012 cm-2, provided the field plate structure is adopted, while the breakdown voltage shows a sudden drop for the defect density over 5×1011 cm-2 without the field plate. This result shows that the field plate structure is effective for suppressing the surface charge influence on breakdown voltage due to the relaxation of the electric field concentration in the surface portion of the AlGaN layer. View full abstract»

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  • Measurements of unity gain cutoff frequency and saturation velocity of a GaN HEMT transistor

    Page(s): 165 - 169
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    The measured intrinsic saturation velocity (vsi) of carriers in a gallium nitride (GaN) high electron mobility transistor (HEMT) is very much lower than that predicted using Monte Carlo simulation. A novel method of extraction of the intrinsic saturation velocity (vsi) of carriers has been developed utilising the deembedded s-parameters, thus enabling the calculation of vsi over a wide range of bias conditions. The method is equally applicable for gallium arsenide (GaAs) and indium phosphide (InP) based transistors. The measurements indicate for GaN-based HEMT a maximum deembedded saturation velocity of 1.1×105 m/s close to the pinchoff voltage (VP). It was found that self-heating had only a weak effect on the saturation velocity up to junction temperatures approaching 140°C above ambient. View full abstract»

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  • Modeling the electrical characteristics of Schottky contacts in low-dimensional heterostructure devices

    Page(s): 170 - 175
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    This paper deals with the modeling of the electronic characteristics of semiconductor devices based on Schottky contacts in low-dimensional systems. For the capacitance-voltage characteristics, a quasi-two-dimensional quantum mechanical model is developed and validated. For the current-voltage characteristics, a unified model is presented, considering both the tunneling as well as the thermionic emission mechanisms. Our theoretical predictions suggest that for photodetection applications the use of these contacts, replacing conventional metal-semiconductor junctions, can reduce the dark current by at least one order of magnitude. View full abstract»

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  • Analysis and synthesis of on-chip spiral inductors

    Page(s): 176 - 182
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    This paper presents a physically based compact model for estimating high-frequency performance of spiral inductors. The model accurately accounts for skin and proximity effects in the metal conductors as well as eddy current losses in the substrate. The model shows excellent agreement with measured data mostly within 10% across a variety of inductor geometries and substrate dopings up to 20 GHz. A web-based spiral inductor synthesis and analysis tool COILS, which makes use of the compact models, is presented. An optimization algorithm using binary searches speeds up the synthesis of inductor designs. View full abstract»

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  • Cellular nonlinear network based on semiconductor tunneling nanostructure

    Page(s): 183 - 189
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    We propose and analyze a cellular nonlinear network (CNN) based on a semiconductor nanostructure consisting of multiple layers of two semiconductors along with an incorporated quantum dot layer. An elementary logic cell of the proposed CNN consists of two resonant tunneling diodes connected in series through a quantum dot. The cell may be realized with multiple layers of two semiconductor materials with an embedded dot layer in between. The local interconnections of nanocells are achieved via tunneling between the neighboring quantum dots. Cells may be biased by the common column contacts, and only edge cells have individual I/O ports. Using approximate tunneling characteristics, we simulated network dynamics and found procedures leading to useful logic functionality. In order to illustrate network capabilities for image processing, we present examples of filtering, erosion, dilation, and edge detection carried out on a test image on a 400×269 cell template. The realization of a number of logic functions in one module is possible due to the incorporation of nonlinear (tunneling) elements for cell interconnections. The proposed CNN architecture for nanostructures demonstrates powerful computing potential that will be beneficial for many practical applications. View full abstract»

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  • Reduction of power consumption in compact DFD display by using FS color technology

    Page(s): 190 - 193
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    A method to drastically reduce the power consumption of the backlight in a compact depth-fused three-dimensional display, which consists of a stack of two liquid crystal (LC) panels, is proposed and experimentally validated. To remove the color filters in the LC panels, we introduced the field-sequential technique for color display. The transmittance of the display could be improved by more than one order. Therefore, the luminance of the backlight could be reduced to less than that of a two-dimensional LC display. View full abstract»

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  • High brightness ZnS and GaN electroluminescent devices using PZT thick dielectric layers

    Page(s): 194 - 203
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    An improved thick dielectric (TD) layer for inorganic electroluminescent (EL) display devices has been achieved through a composite high-κ dielectric sol-gel/powder route. This composite TD film results in a luminance improvement (up to 10×) in these TDEL devices with Eu-doped GaN and Mn-doped ZnS phosphor layers. The use of a composite TD film, composed primarily of lead-zirconate-titanate (PZT), results in a significantly higher charge (>3 μC/cm2) coupling to the phosphor layer. Furthermore, the reduction in porosity of the TD has improved the homogeneity of electric field applied to the phosphor layer, resulting in a steeper luminance-voltage slope. The reduction in porosity has also decreased the diffuse reflection of the TD, which when pigmented, exhibits a diffuse reflectivity of <2% resulting in high display contrast. High luminance levels of up to 3500 cd/m2 have been achieved from the ZnS:Mn TDEL devices and 450 cd/m2 from GaN:Eu devices. A detailed analysis of the electrical steady-state time-varying characteristics has shown that the electrical performance of TDELs is very similar to TFELs in spite of the physical asymmetry in the device structure. These results demonstrate that three critical requirements for practicality of the TDEL approach (formation on standard display glass, low reflectivity, and electric field homogeneity) can be obtained by careful selection and design of the device materials, fabrication process and device structure. View full abstract»

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  • Characterization and modeling of three-terminal heterojunction phototransistors using an InGaP layer for passivation

    Page(s): 204 - 210
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    Fabrication, characterization, and modeling of three-terminal (3T) heterojunction phototransistors (HPTs) using an InGaP layer for passivation (called P-HPTs) compared with similar nonpassivated devices (called NP-HPTs) were reported. Effects of the base passivated by the InGaP layer on devices optical and electrical performance were investigated. In addition to improving the dc current gain in the small current regime, the photocurrent (Iph) and responsivity from the p-i-n diode formed by the base, collector, and subcollector are also enhanced in a P-HPT. The measured optical gains are 45 and 27 for a P- and an NP-HPT under 8.62-μW optical injection operated as a two-terminal (2T) device with a floating base. When the base bias is applied from a voltage source, both 3T P- and NP-HPTs exhibit degraded optical gains. Although a voltage source applied to the base can be used to push the operating point of a heterojunction bipolar transistor to a higher collector current where the current gain is higher, only a small portion of the photocurrent generated within the base-collector region is injected across the base-emitter junction to be amplified. When the base of an HPT is biased using a current source, the Iph and enhanced dc current gain mainly determine both collector photocurrent and optical gain. Thus, a P-HPT biased using a current source shows the best optical performance. Furthermore, the conventional Ebers-Moll equivalent-circuit model was extended to provide simulated results in good agreement with experiment. View full abstract»

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  • Influence of dielectric breakdown on MOSFET drain current

    Page(s): 211 - 217
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    Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 μm. View full abstract»

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  • The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

    Page(s): 218 - 226
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    We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification and production of the smallest 6-T SRAM bitcell reported in 0.13-μm CMOS technology. No additional processing steps were employed in accomplishing this result. Such a methodology is being extended also to subsequent technology generations. The development efforts included the electrical evaluation of several candidate 6-T SRAM bitcell architectures for both high-density and high-speed applications. Based on the electrical evaluations, the chosen cell architectures were incorporated in silicon and verified for their robustness with respect to critical design rules, yields and reliability. The methodology for optical proximity correction for bitcell development has been described here. Minor process enhancements to ensure compatibility of the overall process flow with the SRAM bitcells are described. The use of SRAM-specific electrical test structures serves an important role in validating the electrical performance and confirming the robustness of the bitcells in a manufacturing environment. The monitoring of Vddmin, the minimum voltage at which the memory is functional was used to drive overall process improvements and reliability. Lastly, measurements of soft error rates demonstrated excellent immunity of the bitcells to single event upsets. View full abstract»

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  • Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation

    Page(s): 227 - 236
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    The ultimate limits in scaling of conventional MOSFET devices have led the researchers from all over the world to look for novel device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. These novel devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI devices, dual-gate MOSFETs and in FinFET devices, quantum-mechanical size quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in key device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based device simulator. We also investigate the influence of unintentional doping on the operation of this device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the threshold voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the device drive current and the fluctuations in the device threshold voltage. View full abstract»

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  • Device optimization for digital subthreshold logic operation

    Page(s): 237 - 247
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    Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region. View full abstract»

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  • On the operation configuration of SiGe HBTs based on power gain analysis

    Page(s): 248 - 255
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    The power gain difference, under different device stability conditions, between common-emitter (CE) and common-base (CB) bipolar junction transistors (BJT) is analyzed comprehensively. The analysis reveals that the CB configuration offers higher maximum available power gain than the CE configuration in the device's high operation frequency range, while the inverse relation holds in the very low frequency range. In the intermediate frequency range, the base resistance value, mainly affected by the base doping concentration, determines which configuration offers higher maximum stable power gain (MSG). These analyses have explicit implications on the operation configurations of SiGe heterojunction bipolar transistors (HBTs). Employing a typical doping profile of Si bipolar junction transistors with a trapezoidal Ge profile in SiGe HBTs usually results in a larger base resistance than the emitter resistance. For these devices, the CE configuration exhibits higher MSG than the CB configuration. Employing a higher base doping concentration than the emitter with a box-type Ge profile considerably reduces the base resistance and thus favors the CB configuration for power amplification in this frequency range. The analysis are quantitatively verified with simulation and measurement results from SiGe HBTs of representative Ge and base doping profiles. View full abstract»

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  • Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

    Page(s): 256 - 262
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    We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved. View full abstract»

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  • On the threshold Voltage of strained-Si-Si1-xGex MOSFETs

    Page(s): 263 - 268
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    The threshold voltage shifts (ΔVt(SS) relative to Vt of Si-control devices) in strained-Si-Si1-xGex (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of ΔVt(SS), whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of ΔVt(SS). Models for ΔVt(SS) dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced Vtn(SS) for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of Vtp(SS). View full abstract»

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  • Weave patterned organic transistors on fiber for E-textiles

    Page(s): 269 - 275
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    Flexible transistors were formed directly on fibers in a novel weave-masking fabrication process. Pentacene fiber transistors exhibit mobilities of >0.5 cm2/V-s measured at 20 V VDD and operate stably under a wide range of flexion stress. Devices are defined and positioned solely by a weaving pattern, meaning that simple circuits could potentially be directly built into fabric during manufacturing. This development offers a novel approach for providing information routing within fabric, which is currently a major hurdle in electronic textile development. View full abstract»

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  • Experimental behavior of single-chip IGBT and COOLMOS devices under repetitive short-circuit conditions

    Page(s): 276 - 283
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    This work presents the behavior of single-chip insulated gate bipolar transistors (IGBT) devices under repetitive short-circuit operations. The 600 and 1200 V nonpunch through IGBTs as well as 600 V COOLMOS (trademark of Infineon Technologies) have been tested. The repetition of these severe working conditions is responsible for devices ageing, and results unavoidably in the components failure. A series of experimental tests were made in order to determine the number of short-circuit operations the devices can support before failure for different dissipated energies. The temperature influence has been also investigated. Results show two distinct failure modes depending on the dissipated energy during the tests. A critical value of short-circuit energy has been pointed out which separates these failure modes. Experimental and numerical investigations have been carried out in order to analyze these failure modes. A detailed analysis of the physical mechanisms occurring during the short-circuit failures for dissipated energies equal or lightly higher than the critical value is presented. View full abstract»

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  • Polar heterostructure for multifunction devices: theoretical studies

    Page(s): 284 - 293
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    We examine the potential of devices based on heterostructures made from highly polar materials and semiconductors. Our calculations show that such functional devices have superior sensor properties and transistor properties. The basis device examined is based on the use of a thin oxide with high piezoelectric coefficients or pyroelectric coefficients under the gate region. Channel charge and current are controlled by gate voltage, temperature, or stress. We examine the performance of three classes of heterostructures that form the basis of important semiconductor technologies: 1) Si-SiO2-BaTiO3 heterostructure junctions that would be an important breakthrough for silicon sensor technology; 2) GaN-AlN-BaTiO3 heterostructure junctions that would be important especially in high temperature sensor application; and 3) GaAs-AlGaAs-BaTiO3 heterostructure field effect transistors. The calculations show that with a very thin polar material layer we can have a highly sensitive sensor and transistor. For optimum performance, the polar material (piezoelectric or pyroelectric) layer thickness should be ∼30 Å. View full abstract»

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  • Special issue on non-classical Si CMOS devices and technologies: Extending the roadmap

    Page(s): 294
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  • Electron Devices Society Archival Collection on DVD

    Page(s): 295
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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology