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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Jan. 2005

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Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2005, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
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  • The CSI multimedia architecture

    Publication Year: 2005, Page(s):1 - 13
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (755 KB) | HTML iconHTML

    An instruction set extension designed to accelerate multimedia applications is presented and evaluated. In the proposed complex streamed instruction (CSI) set, a single instruction can process vector data streams of arbitrary length and stride and combines complex memory accesses (with implicit prefetching), program control for vector sectioning, and complex computations on multiple data in a sing... View full abstract»

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  • Execution cache-based microarchitecture for power-efficient superscalar processors

    Publication Year: 2005, Page(s):14 - 26
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB) | HTML iconHTML

    This paper investigates a possible solution to the problem of power consumption in superscalar, out-of-order processors by proposing a new microarchitecture, specifically designed to reduce increasing power requirements of high-end processors. More precisely, we show that by modifying the well-established superscalar processor architecture, significant savings can be achieved in terms of power con... View full abstract»

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  • A process-tolerant cache architecture for improved yield in nanoscale technologies

    Publication Year: 2005, Page(s):27 - 38
    Cited by:  Papers (118)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB) | HTML iconHTML

    Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memor... View full abstract»

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  • Optimum and heuristic synthesis of multiple word-length architectures

    Publication Year: 2005, Page(s):39 - 57
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB) | HTML iconHTML

    This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interaction between scheduling, allocation, and binding, are complicated by the existence of multiple word-length operators. Both optimum and heuristic approaches to the combined problem are f... View full abstract»

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  • Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations

    Publication Year: 2005, Page(s):58 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (815 KB) | HTML iconHTML

    The designs of application specific integrated circuits and/or multiprocessor systems are usually required in order to improve the performance of multidimensional applications such as digital-image processing and computer vision. Wavelet-based algorithms have been found promising among these applications due to the features of hierarchical signal analysis and multiresolution analysis. Because of t... View full abstract»

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  • Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors

    Publication Year: 2005, Page(s):75 - 85
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB) | HTML iconHTML

    We propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorplan. Two complementary methods-FU ordering with submodule design and issue pattern management-are al... View full abstract»

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  • Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers

    Publication Year: 2005, Page(s):86 - 95
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1313 KB) | HTML iconHTML

    High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maint... View full abstract»

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  • Layout techniques for FPGA switch blocks

    Publication Year: 2005, Page(s):96 - 105
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB) | HTML iconHTML

    This paper presents abstract layout techniques for a variety of field-programmable gate array switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks and good results for large switch blocks. We show how it is possible to transform un... View full abstract»

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  • On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

    Publication Year: 2005, Page(s):106 - 125
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (799 KB) | HTML iconHTML

    Although the notion of the parallelism in multidimensional applications has existed for a long time, it is so far unknown what the bound (if any) of inter-iteration parallelism in multirate multidimensional digital signal processing (DSP) algorithms is, and whether the maximum inter-iteration parallelism can be achieved for arbitrary multirate data flow algorithms. This paper explores the bound of... View full abstract»

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  • A robust self-calibrating transmission scheme for on-chip networks

    Publication Year: 2005, Page(s):126 - 139
    Cited by:  Papers (47)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB) | HTML iconHTML

    Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale m... View full abstract»

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  • Synchronization overhead in SOC compressed test

    Publication Year: 2005, Page(s):140 - 152
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (818 KB) | HTML iconHTML

    Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-chip. This paper analyzes the sources of synchronizat... View full abstract»

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  • VLSI implementation of new arithmetic residue to binary decoders

    Publication Year: 2005, Page(s):153 - 158
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    This paper introduces two arithmetic decoders that decode the residue number system into its binary equivalent. The first one deals with the moduli set: (2/sup n/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), while the other deals with the moduli set: (2/sup n+1/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), where n is odd. Compact forms ... View full abstract»

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  • Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

    Publication Year: 2005, Page(s):158 - 162
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using t... View full abstract»

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  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 163
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  • International Symposium on Low Power Electronics and Design (ISLPED'05)

    Publication Year: 2005, Page(s): 164
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  • Quality without compromise [advertisement]

    Publication Year: 2005, Page(s): 165
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  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2005, Page(s): 166
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  • IEEE copyright form

    Publication Year: 2005, Page(s):167 - 168
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu