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IEEE Transactions on Computers

Issue 2 • Date Feb. 2005

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Displaying Results 1 - 20 of 20
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • Editor's note

    Publication Year: 2005, Page(s): 97
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  • Low complexity word-level sequential normal basis multipliers

    Publication Year: 2005, Page(s):98 - 110
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1856 KB) | HTML iconHTML

    For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous. In this paper, two classes of architectures for multipliers over the finite field GF(2m) are proposed. These multipliers are of sequential type, i.e., after receiving the coordinates of the two input field elements, they go through k, 1 ≤ k ≤ m, iterations (i.e., cloc... View full abstract»

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  • Secondary radix recodings for higher radix multipliers

    Publication Year: 2005, Page(s):111 - 123
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB) | HTML iconHTML

    For progressively higher radices, the reduction in partial products obtained by the well-known modified Booth multiplier recoding is offset by the need to precompute a rapidly increasing store of odd multiples of the multiplicand as inputs to each partial product generator (PPG). We propose secondary radix multiplier recoding schemes reducing the number of odd multiples required in the store for v... View full abstract»

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  • Left-to-right optimal signed-binary representation of a pair of integers

    Publication Year: 2005, Page(s):124 - 131
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    The common computation in elliptic curve cryptography (ECC), aP + bQ, is performed by extending Shamir's method for the computation of the product of powers of two elements in a group. The complexity of computing aP + bQ is dependent on the joint weight of the binary expansion of positive integers a and b. We give a method of finding a minimum joint weight signed-binary representation of a pair of... View full abstract»

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  • Uniprocessor performance enhancement through adaptive clock frequency control

    Publication Year: 2005, Page(s):132 - 140
    Cited by:  Papers (16)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB) | HTML iconHTML

    Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock frequency and, hence, performance. However, much more performance can be obtained under typical operating conditions through experimentation, but such increased frequency operation is subject to the possibility of system failure and, hence, data loss/corruption. Further, mobile CPUs such as those in... View full abstract»

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  • Area and system clock effects on SMT/CMP throughput

    Publication Year: 2005, Page(s):141 - 152
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB) | HTML iconHTML

    Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multithreading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide... View full abstract»

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  • Low cost and high speed embedded two-rail code checker

    Publication Year: 2005, Page(s):153 - 164
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1328 KB) | HTML iconHTML

    We propose a compact, high-speed, and highly testable parallel two-rail code checker, particularly suitable to implementing embedded checkers. In fact, it requires only two input codewords to satisfy the totally-self-checking or strongly code-disjoint property with respect to a wide set of realistic internal faults. Our checker can be employed to check the correct operation of a connected function... View full abstract»

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  • Conditional diagnosability measures for large multiprocessor systems

    Publication Year: 2005, Page(s):165 - 175
    Cited by:  Papers (98)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    Diagnosability has played an important role in the reliability of an interconnection network. The classical problem of fault diagnosis is discussed widely and the diagnosability of many well-known networks have been explored. We introduce a new measure of diagnosability, called conditional diagnosability, by restricting that any faulty set cannot contain all the neighbors of any vertex in the grap... View full abstract»

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  • The t/k-diagnosability of the BC graphs

    Publication Year: 2005, Page(s):176 - 184
    Cited by:  Papers (66)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Processor fault diagnosis takes an important role in fault-tolerant computing on multiprocessor systems. There are two classical diagnosis strategies - the precise strategy and the pessimistic strategy, both of which are based on the well-known PMC diagnostic model. Nevertheless, the degree of diagnosability of the system is limited under these two strategies. A better method, called the t/k-diagn... View full abstract»

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  • Line size adaptivity analysis of parameterized loop nests for direct mapped data cache

    Publication Year: 2005, Page(s):185 - 197
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB) | HTML iconHTML

    Caches are crucial components of modern processors; they allow high-performance processors to access data fast and, due to their small sizes, they enable low-power processors to save energy - by circumventing memory accesses. We examine efficient utilization of data caches in an adaptive memory hierarchy. We exploit data reuse through the static analysis of cache-line size adaptivity. We present a... View full abstract»

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  • Efficient reclaiming in reservation-based real-time systems with variable execution times

    Publication Year: 2005, Page(s):198 - 213
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB) | HTML iconHTML Multimedia Media

    We present a general CPU scheduling methodology for managing overruns in a real-time environment, where tasks may have different criticality, flexible timing constraints, shared resources, and variable execution times. The proposed method enhances, the constant bandwidth server (CBS) by providing two important extensions. First, it includes an efficient bandwidth sharing mechanism that reclaims th... View full abstract»

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  • A novel high-order tree for secure multicast key management

    Publication Year: 2005, Page(s):214 - 224
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB) | HTML iconHTML

    Multicast is used to deliver packets to a group of users. To prevent users outside the group from eavesdropping, a group key is maintained to encrypt the group communication, and the group key is changed (rekeying) when a new member joins the group or an existing member leaves the group. Rekeying costs could be as high as n for a group with n members. The hierarchical key-tree approach is widely u... View full abstract»

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  • High-speed parallel-prefix VLSI Ling adders

    Publication Year: 2005, Page(s):225 - 231
    Cited by:  Papers (51)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1296 KB) | HTML iconHTML

    Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. A novel framework is introduced, which allows the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of implementation compared to the parallel-prefix structures proposed for the traditional definition of carry lookahead equations and... View full abstract»

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  • Bounds on the capacity of the unidirectional channels

    Publication Year: 2005, Page(s):232 - 235
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    In the usual binary symmetric channel, both 1→0 and 0→1 types of errors can occur. In the binary asymmetric channel, only 1→0 type of errors can occur, whereas, in the unidirectional channel, both 1→0 and 0→1 types of errors can occur, but, unlike the binary symmetric channel, for any particular transmitted word of length n, all the errors are of the same type. In general,... View full abstract»

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  • Bound-set preserving ROBDD variable orderings may not be optimum

    Publication Year: 2005, Page(s):236 - 237
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    This paper reports a result concerning the relation between the best variable orderings of an ROBDD Gf and the decomposition structure of the Boolean function f represented by Gf. It was stated in [S.-W. Jeong (1992)] that, if f has a decomposition of type f(X)-g(h1(Y1),h2(Y2),...hk(Yk)), where {Y1},... View full abstract»

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  • Preventing session table explosion in packet inspection computers

    Publication Year: 2005, Page(s):238 - 240
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    We first show that various network attacks can cause fatal inflation of dynamic memory usage on packet processing computers. Considering Transmission control protocol (TCP) is utilized by most of these attacks as well as legitimate traffic, we propose a parsimonious memory management guideline based on the design of the TCP and the analysis of real-life Internet traces. In particular, we demonstra... View full abstract»

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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org