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Device and Materials Reliability, IEEE Transactions on

Issue 3 • Date Sept. 2004

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Displaying Results 1 - 25 of 41
  • [Front cover]

    Page(s): c1
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  • IEEE Transactions on Device and Materials Reliability publication information

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  • Table of contents

    Page(s): 297 - 298
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  • Future directions and challenges for ETox flash memory scaling

    Page(s): 301 - 305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    The physical and electrical scaling challenges for ETox™ Flash memory, including reliability considerations, will be reviewed with potential directions for solutions identified. As Flash scales into the sub-100-nm regime, challenges arise due to the high voltage/field requirement of the programming and erase mechanisms and the stringent charge storage requirement of the dielectrics. These challenges will be overcome with innovations in new materials, new cell structures, and memory error management. Using these techniques will extend the viability of Flash memory to at least the 45-nm generation. View full abstract»

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  • Modeling of tunneling current and gate dielectric reliability for nonvolatile memory devices

    Page(s): 306 - 319
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    We present a hierarchy of tunneling models suitable for the two- and three-dimensional simulation of logic and nonvolatile semiconductor memory devices. The crucial modeling topics are comprehensively discussed, namely, the modeling of the energy distribution function in the channel to account for hot-carrier tunneling, the calculation of the transmission coefficient of single and layered dielectrics, the influence of quasi-bound states in the inversion layer, the modeling of static and transient defect-assisted tunneling, and the modeling of dielectric degradation and breakdown. We propose a set of models to link the gate leakage to the creation of traps in the dielectric layer, the threshold voltage shift, and eventual dielectric breakdown. The simulation results are compared to commonly used compact models and measurements of logic and nonvolatile memory devices. View full abstract»

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  • A comparative study of characterization techniques for oxide reliability in flash memories

    Page(s): 320 - 326
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    We compare two different methods for extracting the leakage distribution from accelerated data-retention experiments. It is shown that the equivalent-cell (EC) scheme, which provides a fast estimation of leakage distribution in the array, is totally accurate as compared to a more detailed analysis of single memory cells within the array. The fair agreement between the results of the two characterization schemes is explained, and advantages of the EC technique for fast reliability monitoring in Flash memories are discussed. View full abstract»

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  • Performance, degradation monitors, and reliability of the CHISEL injection regime

    Page(s): 327 - 334
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    This work reviews recent results concerning the performance and reliability of the channel initiated secondary electron (CHISEL) injection regime, often used to boost the programming speed of Flash memories. In order to relate the CHISEL behavior to the physical conditions existing in the device, the injection efficiency of CHISEL is studied on single transistors. A comparison between the degradation in the CHISEL injection and in the channel hot electron (CHE) stress regime has been also performed, and the most relevant electrical monitor for the degradation is assessed. It is confirmed that the CHISEL mechanism is promising for the realization of faster and more efficient Flash memory cells. View full abstract»

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  • Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling

    Page(s): 335 - 344
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    Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed. View full abstract»

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  • Write/erase cycling endurance of memory cells with SiO2/HfO2 tunnel dielectric

    Page(s): 345 - 352
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO2/HfO2 dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after ∼1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO2/HfO2 stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window. View full abstract»

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  • Reliability of pFET EEPROM with 70-Å tunnel oxide manufactured in generic logic CMOS Processes

    Page(s): 353 - 358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    We investigate the reliability of pFET-based EEPROMs with 70-Å tunneling oxides fabricated in standard foundry 0.35-μm, 0.25-μm, and 0.18-μm logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-Å oxide. View full abstract»

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  • A review of ionizing radiation effects in floating gate memories

    Page(s): 359 - 370
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    The effects of ionizing radiation on microelectronics are traditionally a concern for devices intended for the space use, but they are becoming important even at ground level. Ionizing radiation effects can be broadly divided in two classes: total ionizing dose (progressive buildup of defects) and single event effects (macroscopic result of a single microscopic event). In both cases, ionizing radiation can lead to severe degradation of device performance, possibly resulting in device failure. This work is a review of literature results concerning both classes of ionizing radiation-related phenomena on floating gate memories. Regardless of its nature, ionizing radiation impacts two aspects of the performance and reliability of floating gate memories: the functionality and the adherence to specifications of the control circuitry, and the degradation of stored information in the array itself. View full abstract»

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  • Flash memory under cosmic and alpha irradiation

    Page(s): 371 - 376
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Neutron and proton irradiation to simulate cosmic ray jeopardy were used to establish that NOR Flash memory (conventional floating polySi gate or ONO floating gate MirrorBit) soft error failure rate (cross section) is 3-5 orders of magnitude better than SRAM. Flash memory soft error rate for a given dose of alpha particle irradiation is much less than for the same dose from simulated cosmic rays. View full abstract»

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  • Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

    Page(s): 377 - 389
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated. View full abstract»

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  • Improving floating-gate memory reliability by nanocrystal storage and pulsed tunnel programming

    Page(s): 390 - 396
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    Nanocrystal memories have attracted considerable attentions in the last few years as one of the simplest evolution of the standard Flash technology allowing for improved reliability and scaling perspectives. The possibility for a significant thickness reduction for the oxides insulating the floating-gate layer in the memory cell is assured by the discrete storage effect, limiting the impact of stress-induced leakage current on data retention. In this paper we show at the array level that large improvements in anomalous cell occurrence after cycling is encountered for nanocrystal memories with thin tunnel oxide. Further improvements in array reliability is observed adopting a fast pulsed programming, limiting the defect generation rate by a proper definition of the programming waveform. View full abstract»

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  • The two-bit NROM reliability

    Page(s): 397 - 403
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    Saifun NROM™ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM technology is able to provide code flash, data flash, embedded flash, and true EEPROM functionality with a single fabrication process and minor architectural adjustments. Reliability topics of NROM technology are discussed, focusing on the ability to achieve 10-year data retention after 105 program and erase cycles. The accumulated knowledge of NROM physics allows this technology to successfully compete with the industry standard floating-gate memory technology and to gain the acceptance of the memory market. View full abstract»

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  • Data retention reliability model of NROM nonvolatile memory products

    Page(s): 404 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests. View full abstract»

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  • Evaluation of SiO2 antifuse in a 3D-OTP memory

    Page(s): 416 - 421
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1200 KB) |  | HTML iconHTML  

    We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO2 antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving. View full abstract»

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  • Reliability study of phase-change nonvolatile memories

    Page(s): 422 - 427
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110°C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 1011 programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells. View full abstract»

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  • Demonstrated reliability of 4-mb MRAM

    Page(s): 428 - 435
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    The successful commercialization of MRAM will rely on providing customers with a robust and reliable memory product. The intrinsic reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM are two areas of great interest due to the new materials involved in this emerging technology. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating condition. For metal interconnect system, the initial results of Cu with magnetic cladding have met the reliability performance of typical nonclad Cu backend process in electromigration (EM) and iso-thermal annealing (ITA). Finally data retention is demonstrated over times orders of magnitude longer than 10 years. View full abstract»

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  • Reliability properties of low-voltage ferroelectric capacitors and memory arrays

    Page(s): 436 - 449
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1208 KB) |  | HTML iconHTML  

    We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows ∼1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 1013 write/read polarization switching cycles. Retention measured after 1012 switching cycles demonstrates no degradation relative to arrays with minimal cycling. View full abstract»

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  • Dynamic study of the physical processes in the intrinsic line electromigration of deep-submicron copper and aluminum interconnects

    Page(s): 450 - 456
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    Various physical mechanisms are involved in an electromigration (EM) process occurring in metal thin film. These mechanisms are electron-wind force induced migration, thermomigration due to temperature gradient, stressmigration due to stress gradient, and surface migration due to surface tension in the case where free surface is available. In this work, a finite element model combining all the aforementioned massflow processes was developed to study the behaviors of these physical mechanisms and their interactions in an EM process for both Al and Cu interconnects. The simulation results show that the intrinsic EM damage in Al is mainly driven by the electron-wind force, and thus the electron-wind force induced flux divergence is the dominant cause of Al EM failure. On the other hand, the intrinsic EM damage in Cu is driven initially by the thermomigration, and the electron-wind force dominates the EM failure only at a latter stage. This shows that the early stage of void growth in Cu interconnects is more prone to thermomigration than Al. View full abstract»

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  • A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs

    Page(s): 457 - 466
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as τ(Id/W)2∝(Isub/Id)-m. The formula is different from the conventional τId/W-Isub/Id model in that the exponent of Id/W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical τ-Isub/W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases. View full abstract»

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  • Copper trace cracking of BGA packages under die perimeter: combined effect of mold compound and die attach materials

    Page(s): 467 - 481
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    This research examines the combined effect of mold and epoxy die attach materials on the cracking formation of fine copper traces routed under the die perimeters of plastic BGA packages, and under different thermal ramping rates. A designed plastic BGA package with specific traces routed and coupled with the active silicon device procured is used. The objective is accomplished by the use of the methods of finite elemental analysis coupled with a full factorial material experiment. For the JEDEC's MRT L3 and TC Condition B reliability stressing, it is found that a lower CTE and a lower dynamic tensile modulus combination of both mold and die attach materials tends to reduce the occurrence of trace cracking, while the effect of thermal ramping rate is found to be insignificant until 1000 cycles of TC is exceeded. Furthermore, a detailed failure analysis is performed on the stressed parts through continuity testing, mold decapsulation, high magnification X-ray, CSAM, SEM, and parallel polishing to confirm the modeling results and experimental findings. View full abstract»

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  • Dependence of process parameters on stress generation in aluminum thin films

    Page(s): 482 - 487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB) |  | HTML iconHTML  

    The dependence of residual stress on the process parameters for aluminum metallization has been studied using a rotating beam sensor. This shows increasing tensile stress with both the target power and ambient pressure used during the sputter deposition of the aluminum layer. The bulk resistivity of the deposited aluminum has been measured using a Van der Pauw technique on test structures fabricated alongside the sensors and this shows different trends with respect to the target power and ambient pressure. This indicates that the stress in an interconnect feature is dominated by extrinsic components, which result from the mismatch in thermal expansion coefficient between the constituent layers, rather than the defects formed during the sputter deposition of the metallization. This indicates the suitability of the stress sensor technique to the monitoring of interconnect features in a production line environment. View full abstract»

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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

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Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.