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IEEE Transactions on Electronics Packaging Manufacturing

Issue 2 • Date April 2004

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Displaying Results 1 - 14 of 14
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Electronics Packaging Manufacturing publication information

    Publication Year: 2004, Page(s): c2
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  • Wafer-applied underfill: flip-chip assembly and reliability

    Publication Year: 2004, Page(s):101 - 108
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3728 KB) | HTML iconHTML

    Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is n... View full abstract»

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  • Direct gravure printing (DGP) method for printing fine-line electrical circuits on ceramics

    Publication Year: 2004, Page(s):109 - 114
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB) | HTML iconHTML

    The tendency toward higher packing densities and higher frequencies for telecommunication devices based on ceramic technology requires smaller dimensions for electrical wiring. Electrical thick-film circuits for ceramic and LTCC-substrates have, up to now, been printed with screen printing, where the printing lines width limit is about 125 μm in mass production. A silicone polymer direct gravur... View full abstract»

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  • Quality and reliability of high aspect-ratio blind microvias formed by laser-assisted seeding mechanism in PCB

    Publication Year: 2004, Page(s):115 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3696 KB) | HTML iconHTML

    The laser-assisted seeding (LAS) mechanism should be able to plate microvias with a high aspect ratio that may not be feasible by conventional electroless plating due to the small via geometry. In particular, the plating of microvias with a high aspect ratio close to one is difficult due to the limited accessibility of chemical solution to the via internal wall surface in conventional plating tech... View full abstract»

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  • Critical variables of solder paste stencil printing for micro-BGA and fine-pitch QFP

    Publication Year: 2004, Page(s):125 - 132
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    Stencil printing continues to be the dominant method of solder deposition in high-volume surface-mount assembly. Control of the amount of solder paste deposited is critical in the case of fine-pitch and ultrafine-pitch surface-mount assembly. The process is still not well understood as indicated by the fact that industry reports 52-71% surface-mount technology (SMT) defects are related to the sold... View full abstract»

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  • Modeling and optimization of via formation in dielectrics by laser ablation using neural networks and genetic algorithms

    Publication Year: 2004, Page(s):133 - 144
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2072 KB) | HTML iconHTML

    Laser ablation is an effective process for forming vias in dielectric layers during the fabrication of multilayer substrates in microsystems packaging. In this paper, vias with diameters of 10-50 μm are ablated in DuPont Kapton E polyimide using an Anvik HexScan 2150 SXE excimer laser operating at 308 nm. A statistical experiment employing a 25-1 fractional factorial design is conduc... View full abstract»

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  • A scheduling heuristic for maximizing wirebonder throughput

    Publication Year: 2004, Page(s):145 - 150
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    Process planning and scheduling is an important part of managing the complex dynamic back end (i.e., test, assembly, and packaging) of the semiconductor manufacturing process. One of the most critical toolsets in the back end in terms of manufacturing capacity and product flow is the wirebonders that electrically connect bare silicon die to lead frames via thin metal wires. We develop two approach... View full abstract»

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  • Quality without compromise [advertisement]

    Publication Year: 2004, Page(s): 151
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004, Page(s): 152
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  • IEEE Transactions on Advanced Packaging - table of contents

    Publication Year: 2004, Page(s):153 - 154
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  • IEEE Transactions on Components and Packaging Technology - table of contents

    Publication Year: 2004, Page(s):155 - 156
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

    Publication Year: 2004, Page(s): c3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Publication Year: 2004, Page(s): c4
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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University