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IEEE Transactions on Computers

Issue 6 • Jun 1991

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Displaying Results 1 - 12 of 12
  • The orientation of modules based on graph decomposition

    Publication Year: 1991, Page(s):774 - 780
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    In the layout stage of VLSI and printed circuit board (PCB) design, after all circuit modules (rectangular) are placed, it is possible to flip the modules so as to reduce the total net length. The authors formulate the orientation of modules as a graph problem and prove it to be NP-complete. The orientation problem is shown to be equivalent to finding a minimum cut of a graph with some arcs of neg... View full abstract»

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  • Time optimal linear schedules for algorithms with uniform dependencies

    Publication Year: 1991, Page(s):723 - 742
    Cited by:  Papers (83)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1696 KB)

    The authors address the problem of identifying optimal linear schedules for uniform dependence algorithms so that their execution time is minimized. Procedures are proposed to solve this problem based on the mathematical solution of a nonlinear optimization problem. The complexity of these procedures is independent of the size of the algorithm. Actually, the complexity is exponential in the dimens... View full abstract»

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  • On synthesizing optimal family of linear systolic arrays for matrix multiplication

    Publication Year: 1991, Page(s):770 - 774
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    The authors describe a family of linear systolic arrays for matrix multiplication exhibiting a tradeoff between local storage and the number of processing elements (PEs). The design consists of processors hooked into a linear array with each processor having storage s, 1⩽sn, for n×n matrix multiplication, where the number of processors e... View full abstract»

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  • Placement of the processors of a hypercube

    Publication Year: 1991, Page(s):714 - 722
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    The authors formalize the problem of minimizing the length of the longest interprocessor wire as the problem of embedding the processors of a hypercube onto a rectangular mesh, so as to minimize the length of longest wire. Where neighboring nodes of the mesh are taken as being at unit distance from one another, and where wires are constrained to be laid out as horizontal and vertical wires, the le... View full abstract»

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  • Automatic test pattern generation with branch testing

    Publication Year: 1991, Page(s):785 - 791
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    The authors present a test algorithm for finite state machines called branch testing. Based on branch testing, a design-for-test (DFT) method is proposed. Comparisons to other DFT methods show the method to be competitive relative to circuit overhead. A minimum set of paths containing all primary and internal gate-level input/output lines is found. Each of these paths is then sensitized so as to d... View full abstract»

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  • Parallel recognition and parsing on the hypercube

    Publication Year: 1991, Page(s):764 - 770
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    The authors present parallel algorithms for recognizing and parsing context-free languages on the hypercube. This algorithm is both time-wise and space-wise optimal with respect to the usual sequential dynamic programming algorithm. Also, the number of nonoverlapping interprocessor data transmissions for the recognition phase is small. It is noted that this is desirable since communication cost in... View full abstract»

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  • Combining logic minimization and folding for PLAs

    Publication Year: 1991, Page(s):706 - 713
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    The authors present an approach that combines logic minimization and folding for a programmable logic array (PLA). An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, the authors model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. This folding algorithm is able to find optimal solutions for th... View full abstract»

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  • A theory of reduced and minimal procedural dependencies

    Publication Year: 1991, Page(s):681 - 692
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1004 KB)

    A reduced set of procedural dependencies is presented which is necessary and sufficient to describe all procedural dependencies in standard imperative codes. Hence, the set is minimal. In conjunction with reduced data dependencies, this set forms a set of minimal semantic dependencies for all traditional code. It is also shown that all forward branches in structured code are procedurally independe... View full abstract»

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  • Generation of digit reversed address sequences for fast Fourier transforms

    Publication Year: 1991, Page(s):780 - 784
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    The hardware design of a circuit capable of producing digit reversed sequences for radix-2, radix-4, and mixed radix-2/4 fast Fourier transform (FFT) algorithms is presented in detail. The design requires selectively routing the output of a binary counter to the output address pointer used during the execution of the FFT. The digit reversed counter is capable of generating address sequences for fa... View full abstract»

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  • A new framework for designing and analyzing BIST techniques and zero aliasing compression

    Publication Year: 1991, Page(s):743 - 763
    Cited by:  Papers (93)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1528 KB)

    A general framework for shift register-based signature analysis is presented, and a mathematical model for this framework-based on coding theory-is developed. There are two key features of this formulation, first, it allows for uniform treatment of LFSR, MISR, and multiple MISR-based signature analyzer. In addition, using this formulation, a new compression scheme for multiple output CUT is propos... View full abstract»

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  • The KYKLOS multicomputer network: interconnection strategies, properties, and applications

    Publication Year: 1991, Page(s):693 - 705
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    A tree-based interconnection architecture (called KYKLOS) for multicomputer systems is proposed. While the general form of the topology consists of multiple m-ary trees sharing a common set of leaf nodes, the focus is on the dual-tree case. One version of the dual-tree KYKLOS involves a bottom tree where the ordering of descendants of nodes at every level is an m-way shuffle. Thi... View full abstract»

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  • Performance analysis of virtual cut-through switching in HARTS: a hexagonal mesh multicomputer

    Publication Year: 1991, Page(s):669 - 680
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The authors present a formal analysis of virtual cut-through in a C-wrapped hexagonal mesh multicomputer, called the HARTS (hexagonal architecture for real-time systems). In virtual cut-through, packets arriving at an intermediate node are forwarded to the next node in the route without buffering if a circuit can be established to the next node. The hexagonal mesh is first characterized using a co... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org