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Electron Device Letters, IEEE

Issue 12 • Date Dec. 2004

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Displaying Results 1 - 25 of 29
  • Table of contents

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Electron Device Letters publication information

    Page(s): c2
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  • Editorial kudos to our reviewers

    Page(s): 753
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  • The Golden List

    Page(s): 754 - 762
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  • Low-κ BCB passivation on AlGaN-GaN HEMT fabrication

    Page(s): 763 - 765
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    Due to the stress-induced polarization effect on the GaN HEMTs, the surface passivation of the device is critical and is deserved to conduct a detailed study. It has been proven that the GaN HEMTs demonstrate nondispersive pulsed current-voltage (I-V) characteristics and better microwave power performances after passivating the Si3N4 film on the GaN surface. In this letter, we proposed to use the BCB material, a negative photoresist with a low-κ characteristic, as the surface passivation layer on GaN HEMTs fabrication. After comparing the dc I-V, pulsed I-V, RF small-signal, microwave power characteristics, and device reliability, this BCB-passivated GaN HEMT achieved better performance than the Si3N4 passivated device. View full abstract»

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  • Two-stage broadband high-gain W-band amplifier using 0.1-μm metamorphic HEMT technology

    Page(s): 766 - 768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    We report broadband high-gain W-band monolithic microwave integrated circuit amplifiers based on 0.1-μm InGaAs-InAlAs-GaAs metamorphic high electron mobility transistor (MHEMT) technology. The amplifiers show excellent S/sub 21/ gains greater than 10 dB in a very broad W-band frequency range of 75-100 GHz, thereby exhibiting a S/sub 21/ gain of 10.1 dB, a S/sub 11/ of -5.1 dB and a S/sub 22/ of -5.2 dB at 100 GHz, respectively. The high gain of the amplifier is mainly attributed to the performance of the MHEMTs exhibiting a maximum transconductance of 691 mS/mm, a current gain cutoff frequency of 189 GHz, and a maximum oscillation frequency of 334 GHz. View full abstract»

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  • Extraction of the average collector velocity in high-speed "Type-II" InP-GaAsSb-InP DHBTs

    Page(s): 769 - 771
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    In "type-II" NpN InP-GaAsSb-InP double heterostructure bipolar transistors DHBTs), the p+ GaAsSb base conduction band edge lies ΔEC above the InP collector conduction band: a small ballistic injection energy ΔEC is thus imparted to electrons as they are launched into the collector. The resulting high initial velocity should in principle reduce the collector signal delay time in comparison to the case where thermal electrons are accelerated by the collector electric field alone. We extract the bias dependence of the average collector electron velocity in high-speed InP-GaAs0.62Sb0.38-InP DHBTs, and find a maximum average velocity reaching 4×107 cm/s across a 2000 Å InP collector. This finding provides evidence of the performance advantage afforded by abrupt type-II base/collector (B/C) junctions for collector transport when compared to other B/C junctions. View full abstract»

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  • GaAs MOSFET using InAlP native oxide as gate dielectric

    Page(s): 772 - 774
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    GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39×10/sup -7/ mA/μm2 at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 μm. Devices with 2-μm-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage. View full abstract»

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  • CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique

    Page(s): 775 - 777
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    This letter reports the first replacement metal gate MOSFETs with chemical vapor deposition (CVD) Rhenium (Re), and physical vapor deposition (PVD) Tantalum (Ta) as the stacked gate electrode. Transistors with PVD Ta electrode are fabricated with a replacement and a nonself-aligned method for comparison. Our data show that CVD Re can be implemented as a gate electrode material for MOS transistors. The CVD Re process has the advantage of reducing the plasma and radiation damages to the gate oxide. A thick layer of PVD Ta covering a thin layer of CVD Re forms the stacked gate structure and makes the metal chemical-mechanical polishing feasible. View full abstract»

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  • Characterization of novel varistor+inductor integrated passive devices

    Page(s): 778 - 780
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    This letter describes the design, modeling, simulation, and fabrication of novel integrated passive devices (IPDs). These IPDs, comprising of a cofired multilayered varistor and inductor, have been developed in the ceramic coprocessing technology. The equivalent model of the new structures is presented, suitable for design and circuit simulations. The fabrication method, new design of structures and patented materials of these devices lead to improved characteristics suitable for application in high-frequency suppressors. The IPDs were tested in the frequency range of 1 MHz-3 GHz using an Agilent 4287A RF LCR meter. The measurements confirm the validity of the proposed model. View full abstract»

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  • Low-frequency noise measurement-based reliability testing of VLSI interconnects with different geometry

    Page(s): 781 - 783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (94 KB) |  | HTML iconHTML  

    Low-frequency noise measurements were performed on thin metallic very large-scale integration (VLSI) interconnects of three different geometries. These measurements were carried out under stressing current densities between 1.0×105 A/cm2 and 2.2×106 A/cm2 at different ambient temperatures up to 280°C, in order to investigate the dependence of low-frequency noise on the geometrical shape of the VLSI interconnects. The behavior of these samples under these conditions is analyzed in this letter. View full abstract»

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  • HfO2 MIS capacitor with copper gate electrode

    Page(s): 784 - 786
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    Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO2 dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO2 dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown (QBD) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO2 dielectric, Cu in contact with HfO2 seems to be very stable. The HfO2 capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO2 with its considerably high density of 9.68 g/cm3 is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes. View full abstract»

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  • Integrated tunable magnetic RF inductor

    Page(s): 787 - 789
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    We demonstrate, for the first time to our knowledge, a passive, electrically tunable integrated radio frequency (RF) inductor based on a planar solenoid with a thin-film ferromagnetic(FM) (NiFe) core. Variation of inductance is achieved by leading an additional dc current through the same device, thereby changing the effective permeability of the FM core. Tuning ranges (relative variations in inductance) of 85%, 35%, and 20% are achieved at 0.1, 1, and 2 GHz, respectively, for inductances in the range of 1 to 150 nH. View full abstract»

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  • 800 V 4H-SiC RESURF-type lateral JFETs

    Page(s): 790 - 791
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    This letter proposes to show that a lateral switching device has some unique advantages, including little dependence on substrate defects, low on-resistance, and a simple design of heat radiation. A reduced surface field (RESURF) type SiC-JFET is one of candidate devices for an electric or hybrid automobile application. Small RESURF-type SiC-JFETs with gate width of 200 μm and a blocking voltage of 800 V were fabricated. The fabrication and characteristics of the devices are described and discussed. View full abstract»

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  • An elastically stretchable TFT circuit

    Page(s): 792 - 794
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    An elastically stretchable, skin-like transistor circuit is demonstrated. The circuit is built on an elastomeric substrate patterned with stretchable gold film interconnects. Inverters were made by surface-mounting flexible amorphous-silicon thin-film transistors on the elastomeric substrate. The electrical performance of the inverters was evaluated prior to, during, and after uni-axial stretching by up to 12%. Performance in the relaxed state before and after stretching was identical. Small changes in circuit performance were seen in the stretched state. This first elastic transistor circuit demonstrates the functionality of stretchable interconnects, and the feasibility of fabricating active circuits on electronic skin. View full abstract»

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  • Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

    Page(s): 795 - 797
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Localized charges in a nitride-trapping device provide two-bit/cell operations. Adding multilevel-cells (MLCs) to the physical bits produces a four-bit/cell device. However, it is difficult to get sufficient sensing windows for MLC operation because the left bit and right bit interfere with each other. This letter analyzes the effect of the second bit effect and investigates parameters affecting the sensing current window for physical four-bit/cell operations. The sensing window is found to increase with a higher reading bias, and also with a higher programmed Vt. However, severe second bit effects set in at high Vt, and decreased the sensing window again. An optimal sensing window is found at moderately high Vt. View full abstract»

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  • Characteristics of body-tied triple-gate pMOSFETs

    Page(s): 798 - 800
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    Body-tied triple-gate pMOSFETs were fabricated using bulk Si wafers and characterized. Process steps to implement the devices are explained briefly. Device characteristics of the triple-gate pMOSFETs were compared with those of the conventional planar channel device. While maintaining low off-leakage currents and threshold voltages similar to those of planar pMOSFETs in the parallel arrayed 30 000 transistors, the body-tied triple-gate MOSFETs showed about 74 mV/dec of subthreshold swing (92 mV/dec for conventional devices) and a drain-induced barrier lowering of 34 mV/V (92 mV/V for conventional devices). It was also addressed that ISUB/ID of the body-tied triple-gate is lower than that of the planar channel device. View full abstract»

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  • Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

    Page(s): 801 - 803
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    This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO2-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of Ion/Ioff without any sign of sublinear upward bending of the IDS--VDS curves at low drain voltage. View full abstract»

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  • Novel FRESURF LDMOSFET devices with improved BVdss-Rdson

    Page(s): 804 - 806
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    In this letter, we propose and demonstrate a novel device based on a floating reduced surface field (FRESURF) concept which allows the realization of significantly higher breakdown voltage in a thin epitaxy-based power IC technology. The newly proposed device with the floating buried layer pulled back from the source side is able to realize an enhanced breakdown voltage (BVdss) without degrading the specific on-resistance (RdsonA). BVdss-RdsonA values like 47 V-0.28 mΩ·cm2 or 93 V-0.82 mΩ·cm2 have been realized with a conventional power IC technology without any added process complexity. View full abstract»

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  • Impact ionization in thin silicon diodes

    Page(s): 807 - 809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    We study the breakdown behavior of thin, abrupt silicon pin-diodes, using a low-power optical technique which can directly measure the avalanche multiplication factors even in the presence of large tunneling currents. Our measurements agree with a simple model for nonlocal avalanche generation, and we use this model to extend the breakdown predictions to a broad class of doped diodes similar to those found in the base-collector region of bipolar devices. Based on this analysis, we make quantitative estimates for the BVCEO breakdown of modern Si and SiGe high-speed bipolar transistors. View full abstract»

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  • Novel dual bit tri-gate charge trapping memory devices

    Page(s): 810 - 812
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    Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range LG=100-220 nm and we focus on their write-erase, retention, and cycling characteristics. View full abstract»

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  • Body effect in tri- and pi-gate SOI MOSFETs

    Page(s): 813 - 815
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    A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate. View full abstract»

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  • A transient analysis method to characterize the trap vertical location in nitride-trapping devices

    Page(s): 816 - 818
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    A new method to probe the trap vertical location for nitride-trapping devices is proposed. This method requires only measuring the time dependence of gate injection at various gate voltages on a single wafer. The transient current (J) and the instantaneous electric field (E) across the top oxide can be directly obtained based on various cases of trap location. Comparisons can be made to check which case has the best consistency for the J versus E behaviors. The only assumption in this method is that the transient current J and the instantaneous E field should follow a consistent tunneling relationship at different gate voltages. The experimental results show unequivocally that electrons are trapped at the interface between top oxide and nitride for oxide grown by thermal conversion. However, for the direct-deposited top oxide the electrons are more spatially distributed in the nitride. This method is a simple and convincing tool to detect the nitride trap vertical location. View full abstract»

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  • Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length

    Page(s): 819 - 821
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V ) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer from severe distortion of C-V due to tunneling current, resulting in poor oxide thickness extraction. The distortion can be suppressed using high frequencies in series model or using short gate lengths in parallel model. Considering instrument limits and manufacturability, however, the parallel model is more desirable. The distortion can be completely suppressed up to 104 A/cm2 of tunneling current, using gate lengths shorter than 0.2 μm in parallel model. View full abstract»

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  • IEEE Electron Devices Society meetings calendar for 2004 (as of 04 November 2004)

    Page(s): 822 - 823
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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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