IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Dec. 2004

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  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Legalizing a placement with minimum total movement

    Publication Year: 2004, Page(s):1597 - 1613
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB) | HTML iconHTML

    Most tools for the placement of very large scale integrated chips work in two steps. First, the cells that have to be placed are roughly spread out over the chip area, ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization). In this pa... View full abstract»

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  • A methodology for the simultaneous design of supply and signal networks

    Publication Year: 2004, Page(s):1614 - 1624
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB) | HTML iconHTML

    We present an early-stage global wire-design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted t... View full abstract»

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  • A universal technique for fast and flexible instruction-set architecture simulation

    Publication Year: 2004, Page(s):1625 - 1639
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB) | HTML iconHTML

    Today, designers of next-generation embedded processors and software are increasingly faced with short product lifetimes. The resulting time-to-market constraints are contradicting the continually growing processor complexity. Nevertheless, an extensive design-space exploration and product verification is indispensable for a successful market launch. In the last decade, instruction-set simulators ... View full abstract»

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  • On the characterization and efficient computation of hard-to-detect bridging faults

    Publication Year: 2004, Page(s):1640 - 1649
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults for test generation efficiently, when it is impractical to target all the bridging faults (or all the realistic bridging faults). We demonstrate that the faults selected based on the proposed characterization are indeed ... View full abstract»

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  • Generation of test patterns without prohibited pattern set

    Publication Year: 2004, Page(s):1650 - 1660
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB) | HTML iconHTML

    This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired pseudorandom quality of the generated test patterns and maintains fault coverage close to the figures achieved with a conventional maximal length linea... View full abstract»

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  • Closed-form delay and slew metrics made easy

    Publication Year: 2004, Page(s):1661 - 1669
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    For optimizations like physical synthesis and static timing analysis, efficient interconnect delay and slew computation is critical. Since one cannot often afford to run asymptotic waveform evaluation (Pillage and Rohrer, 1990), constant time solutions are required. This work presents the first complete solution to closed-form formulas for both delay and also for slew. Our metrics are derived from... View full abstract»

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  • Postroute gate sizing for crosstalk noise reduction

    Publication Year: 2004, Page(s):1670 - 1677
    Cited by:  Papers (10)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets ... View full abstract»

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  • Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics

    Publication Year: 2004, Page(s):1677 - 1683
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. Statistical design methods have been proposed in the past to model the impact of process variations. However, all the existing methods deal almost exclusively with modeling delay variations of logical gates or physical variations of inte... View full abstract»

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  • Retiming-based timing analysis with an application to mincut-based global placement

    Publication Year: 2004, Page(s):1684 - 1692
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (587 KB) | HTML iconHTML

    In this paper, we formulate the physical planning with retiming problem and propose an algorithm called GEO. Our performance-driven global placement algorithm GEO is mincut-based, where a multilevel partitioning is performed recursively to divide the netlist and assign gates to the tiles in a top-down fashion. The contribution of our work is on the development of retiming-aware timing analysis (RT... View full abstract»

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  • An efficient technique for exploring register file size in ASIP design

    Publication Year: 2004, Page(s):1693 - 1699
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Performance estimation is a crucial operation which drives the design space exploration in an application-specific instruction set processor synthesis. With the increase in the level of integration, the design space has considerably expanded, which makes the simulation-driven techniques inadequate due to their slow speed. Alternatively, there are approaches which estimate performance by scheduling... View full abstract»

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  • Special issue on design automation methods and tools for microfludics-based biochips

    Publication Year: 2004, Page(s): 1700
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  • 2004 Index

    Publication Year: 2004, Page(s):1701 - 1718
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  • IEEE Member Digital Library [advertisement]

    Publication Year: 2004, Page(s): 1719
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2004, Page(s): 1720
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu