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IEEE Transactions on Computers

Issue 1 • Jan. 2005

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2005, Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2005, Page(s): c2
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  • Error-detection codes: algorithms and fast implementation

    Publication Year: 2005, Page(s):1 - 11
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (486 KB) | HTML iconHTML Multimedia Media

    Binary CRCs are very effective for error detection, but their software implementation is not very efficient. Thus, many binary nonCRC codes (which are not as strong as CRCs, but can be more efficiently implemented in software) are proposed as alternatives to CRCs. The nonCRC codes include WSC, CXOR, one's-complement checksum, Fletcher checksum, and block-parity code. We present a general algorithm... View full abstract»

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  • A hardware algorithm for modular multiplication/division

    Publication Year: 2005, Page(s):12 - 21
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1135 KB) | HTML iconHTML

    A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out b... View full abstract»

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  • Software Trace Cache

    Publication Year: 2005, Page(s):22 - 35
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB) | HTML iconHTML

    We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimi... View full abstract»

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  • Location-aided flooding: an energy-efficient data dissemination protocol for wireless-sensor networks

    Publication Year: 2005, Page(s):36 - 46
    Cited by:  Papers (66)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB) | HTML iconHTML

    We present a new information dissemination protocol for wireless sensor networks. This protocol uses location information to reduce redundant transmissions, thereby saving energy. The sensor network is divided into virtual grids and each sensor node associates itself with a virtual grid based on its location. Sensor nodes within a virtual grid are classified as either gateway nodes or internal nod... View full abstract»

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  • Real-time dwell scheduling of component-oriented phased array radars

    Publication Year: 2005, Page(s):47 - 60
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1376 KB) | HTML iconHTML

    A multifunction phased array radar must search and track suspicious targets in its surveillance space in a real-time fashion. With inefficient scheduling implementations in many traditional systems, much radar resource is wasted with a very limited performance gain. This paper targets one of the most important issues in the design of modern phased array radars: real-time dwell scheduling. We forma... View full abstract»

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  • The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: mathematical foundations and cost-effective implementations

    Publication Year: 2005, Page(s):61 - 75
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1472 KB) | HTML iconHTML

    Partitioning techniques enable identification of fault-embedding scan cells in scan-based BIST. We introduce deterministic partitioning techniques capable of resolving the location of the fault-embedding scan cells. We outline a complete mathematical analysis that identifies the class of deterministic partitioning structures and complement this rigorous mathematical analysis with an exposition of ... View full abstract»

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  • Cache conscious data layout organization for conflict miss reduction in embedded multimedia applications

    Publication Year: 2005, Page(s):76 - 81
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. We propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce the majority of the conflict c... View full abstract»

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  • Scaling up the Atlas chip-multiprocessor

    Publication Year: 2005, Page(s):82 - 87
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB) | HTML iconHTML

    Atlas, a dynamically multithreading chip-multiprocessor (CMP), gains little complexity as processing elements are added. When the model is scaled up with strategic layouts and realistic latencies, area and power efficiency surpass that of an aggressive out-of-order processor, though results are sensitive to global communication delay. View full abstract»

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  • Parallel decoding cyclic burst error correcting codes

    Publication Year: 2005, Page(s):87 - 92
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB) | HTML iconHTML

    Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Un... View full abstract»

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  • Reviewers list

    Publication Year: 2005, Page(s):93 - 96
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  • TC Information for authors

    Publication Year: 2005, Page(s): c3
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  • [Back cover]

    Publication Year: 2005, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org