By Topic

Computers, IEEE Transactions on

Issue 1 • Date Jan. 2005

Filter Results

Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2005 , Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (142 KB)  
    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2005 , Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (74 KB)  
    Freely Available from IEEE
  • Error-detection codes: algorithms and fast implementation

    Publication Year: 2005 , Page(s): 1 - 11
    Cited by:  Papers (3)
    Multimedia
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (486 KB) |  | HTML iconHTML  

    Binary CRCs are very effective for error detection, but their software implementation is not very efficient. Thus, many binary nonCRC codes (which are not as strong as CRCs, but can be more efficiently implemented in software) are proposed as alternatives to CRCs. The nonCRC codes include WSC, CXOR, one's-complement checksum, Fletcher checksum, and block-parity code. We present a general algorithm for constructing a family of binary error-detection codes. This family is large because it contains all these nonCRC codes, CRCs, perfect codes, as well as other linear and nonlinear codes. In addition to unifying these apparently disparate codes, our algorithm also generates some nonCRC codes that have minimum distance 4 (like CRCs) and efficient software implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A hardware algorithm for modular multiplication/division

    Publication Year: 2005 , Page(s): 12 - 21
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1135 KB)  

    A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n-bit modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software Trace Cache

    Publication Year: 2005 , Page(s): 22 - 35
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB) |  | HTML iconHTML  

    We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimizations. We target not only an improvement in the instruction cache hit rate, but also an increase in the effective fetch width of the fetch engine. The STC algorithm organizes basic blocks into chains trying to make sequentially executed basic blocks reside in consecutive memory positions, then maps the basic block chains in memory to minimize conflict misses in the important sections of the program. We evaluate and analyze in detail the impact of the STC, and code layout optimizations in general, on the three main aspects of fetch performance; the instruction cache hit rate, the effective fetch width, and the branch prediction accuracy. Our results show that layout optimized, codes have some special characteristics that make them more amenable for high-performance instruction fetch. They have a very high rate of not-taken branches and execute long chains of sequential instructions; also, they make very effective use of instruction cache lines, mapping only useful instructions which will execute close in time, increasing both spatial and temporal locality. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Location-aided flooding: an energy-efficient data dissemination protocol for wireless-sensor networks

    Publication Year: 2005 , Page(s): 36 - 46
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (976 KB) |  | HTML iconHTML  

    We present a new information dissemination protocol for wireless sensor networks. This protocol uses location information to reduce redundant transmissions, thereby saving energy. The sensor network is divided into virtual grids and each sensor node associates itself with a virtual grid based on its location. Sensor nodes within a virtual grid are classified as either gateway nodes or internal nodes. While gateway nodes are responsible for forwarding the data across virtual grids, internal nodes forward the data within a virtual grid. The proposed approach, termed location-aided flooding (LAF), achieves energy savings by reducing the redundant transmissions of the same packet by a node. We study the performance of LAF for different grid sizes and different node densities and compare it to other well-known methods. We show that LAF can save a significant amount of energy compared to prior methods. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Real-time dwell scheduling of component-oriented phased array radars

    Publication Year: 2005 , Page(s): 47 - 60
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB) |  | HTML iconHTML  

    A multifunction phased array radar must search and track suspicious targets in its surveillance space in a real-time fashion. With inefficient scheduling implementations in many traditional systems, much radar resource is wasted with a very limited performance gain. This paper targets one of the most important issues in the design of modern phased array radars: real-time dwell scheduling. We formalize the typical workload of a modern phased array radar and propose a rate-based approach to schedule radar dwells in a real-time fashion. We show how to reserve radar resources to guarantee the minimum radar operation without sacrificing the stability of the system. The strength of our approach is verified by a series of simulation experiments based on a real phased array radar for air defense frigates [A. G. Huizing et al. (1996)]. A significant improvement in the performance of phased array radars was shown. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: mathematical foundations and cost-effective implementations

    Publication Year: 2005 , Page(s): 61 - 75
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1472 KB) |  | HTML iconHTML  

    Partitioning techniques enable identification of fault-embedding scan cells in scan-based BIST. We introduce deterministic partitioning techniques capable of resolving the location of the fault-embedding scan cells. We outline a complete mathematical analysis that identifies the class of deterministic partitioning structures and complement this rigorous mathematical analysis with an exposition of the appropriate cost-effective implementation techniques. We validate the superiority of the deterministic techniques both in an average-case sense by conducting simulation experiments and in a worst-case sense through a thorough mathematical analysis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cache conscious data layout organization for conflict miss reduction in embedded multimedia applications

    Publication Year: 2005 , Page(s): 76 - 81
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. We propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce the majority of the conflict cache misses. The focus of this paper is on the formal and heuristic algorithm we use to steer the data layout decisions and the experimental results obtained using a prototype tool. Experiments on real-life demonstrators illustrate that we are able to reduce up to 82 percent of the conflict misses for applications which are already aggressively transformed at source-level. At the same time, we also reduce the off-chip data accesses by up to 78 percent. In addition, we are able to reduce up to 20 percent more conflict misses compared to existing techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scaling up the Atlas chip-multiprocessor

    Publication Year: 2005 , Page(s): 82 - 87
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    Atlas, a dynamically multithreading chip-multiprocessor (CMP), gains little complexity as processing elements are added. When the model is scaled up with strategic layouts and realistic latencies, area and power efficiency surpass that of an aggressive out-of-order processor, though results are sensitive to global communication delay. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel decoding cyclic burst error correcting codes

    Publication Year: 2005 , Page(s): 87 - 92
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reviewers list

    Publication Year: 2005 , Page(s): 93 - 96
    Save to Project icon | Request Permissions | PDF file iconPDF (69 KB)  
    Freely Available from IEEE
  • TC Information for authors

    Publication Year: 2005 , Page(s): c3
    Save to Project icon | Request Permissions | PDF file iconPDF (74 KB)  
    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2005 , Page(s): c4
    Save to Project icon | Request Permissions | PDF file iconPDF (142 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org