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IEE Proceedings - Computers and Digital Techniques

Issue 5 • Date 17 Sept. 2004

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Displaying Results 1 - 7 of 7
  • Fault-tolerant routing in hypercube networks without virtual channels

    Publication Year: 2004, Page(s):377 - 384
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (315 KB)

    A fault-tolerant wormhole routing algorithm for hypercubes without using any virtual channels is presented. The routing algorithm can tolerate any pattern of faulty nodes as long as the number of faulty nodes is no more than n/2, where n is the dimension of the hypercube. Fur... View full abstract»

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  • Word-level symbolic simulation in processor verification

    Publication Year: 2004, Page(s):356 - 366
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (608 KB)

    Formal verification of RT-level digital systems has attracted attention due to its efficiency over traditional simulation methods. This technology is still at its infancy and faces problems of property checking efficiency, memory explosion, and simultaneously the handling of data and control modules of hardware to be verified. Various methods of representing hardware and/or algorithms for property... View full abstract»

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  • Using compiler-generated approximate critical path information to prioritise instructions for value prediction

    Publication Year: 2004, Page(s):321 - 331
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (824 KB)

    One of the potential difficulties in developing cost-effective value prediction mechanisms is determining which instructions should be selected for prediction when the hardware resources are limited. The authors examine a compiler algorithm that statically assigns priorities to instructions using approximate critical path information to identify the best candidates for value prediction. This stati... View full abstract»

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  • Reconfigurable computing for shape-adaptive video processing

    Publication Year: 2004, Page(s):313 - 320
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (628 KB)

    Various reconfigurable computing strategies are examined regarding their suitability for implementing shape-adaptive video processing algorithms of typical object-oriented multimedia applications. The utilisation of reconfigurability at different levels is investigated and the implications of designing reconfigurable shape-adaptive video processing circuits are addressed. Simple models for represe... View full abstract»

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  • Test scheduling with power-time tradeoff and hot-spot avoidance using MILP

    Publication Year: 2004, Page(s):341 - 355
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1384 KB)

    A test scheduling methodology for core-based systems on a chip allows tradeoffs between system power dissipation and overall test time while avoiding the formation of hot-spots. The basic strategy is to use a power profile of nonembedded cores over time and grids to find the best mix of their test pattern subsets that satisfy power and/or time constraints. Two mixed-integer linear programming form... View full abstract»

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  • Generation of processor interface for SoC using standard communication protocol

    Publication Year: 2004, Page(s):367 - 376
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (751 KB)

    System-on-chip synthesis is not a straightforward process; it brings new challenges including the necessity of intellectual property (IP) reuse to shorten the design time. The necessity for the rapid integration of communication logic between modules illustrates the importance of communication synthesis. In the following article, the goal is to allow flexibility and rapid integration of communicat... View full abstract»

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  • Scheduling and allocation using closeness tables

    Publication Year: 2004, Page(s):332 - 340
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (325 KB)

    An heuristic approach towards the scheduling, binding and allocation problem for the high-level synthesis of data-paths is presented. The approach makes use of closeness tables to group operations with similar closeness properties, based on their inputs and outputs, into clusters. A tight packing scheduling and binding algorithm is then used to schedule and bind operations from individual clusters... View full abstract»

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