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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 11 • Nov. 2004

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Displaying Results 1 - 14 of 14
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Reversible cascades with minimal garbage

    Publication Year: 2004, Page(s):1497 - 1509
    Cited by:  Papers (83)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. We start with the analysis of the number of garbage outputs that must be added to a multiple output function to make it reversible. We give a precise formula for the theoretical minimum of the required number of garbage outputs. For some benchmark functions, we calculate the garbage required b... View full abstract»

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  • Nonlinear driver models for timing and noise analysis

    Publication Year: 2004, Page(s):1510 - 1521
    Cited by:  Papers (7)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    This paper presents a novel and flexible modeling technique to generate accurate linear and nonlinear driver models with applications in timing and noise analysis. The new technique, based on Galerkin's finite elements method, is very efficient because it relies on existing logic block characterization for timing, does not require additional nonlinear circuit simulations during modeling, and gener... View full abstract»

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  • Bus-driven floorplanning

    Publication Year: 2004, Page(s):1522 - 1530
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB) | HTML iconHTML

    In this paper, we present an integrated approach for floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus specifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a placement of all circuit blocks such that each bus can be realized as a rectangular strip (horizontal or vertical) going through all the b... View full abstract»

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  • Automated bus generation for multiprocessor SoC design

    Publication Year: 2004, Page(s):1531 - 1549
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB) | HTML iconHTML

    The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global... View full abstract»

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  • Critical path selection for delay fault testing based upon a statistical timing model

    Publication Year: 2004, Page(s):1550 - 1565
    Cited by:  Papers (61)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB) | HTML iconHTML

    Critical path selection is an indispensable step for testing of small-size delay defects. Historically, this step relies on the construction of a set of worst-case paths, where the timing lengths of the paths are calculated based upon discrete-valued timing models. The assumption of discrete-valued timing models may become invalid for modeling delay effects in the deep submicron domain, where the ... View full abstract»

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  • Fair watermarking using combinatorial isolation lemmas

    Publication Year: 2004, Page(s):1566 - 1574
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    Watermarking is one of the most effective mechanisms for intellectual property protection (IPP) of hardware and software artifacts. Numerous watermarking-based IPP techniques have been proposed that satisfy a spectrum of IPP desiderata, including full preservation of functionality, low timing, area and power overhead, transparency to the synthesis and compilation process, and resilience against at... View full abstract»

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  • Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction

    Publication Year: 2004, Page(s):1575 - 1580
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    Fast parasitic extraction is an integral part of high-speed microelectronic simulation at the package and on-chip level. Integral equation methods and related fast solvers for the iterative solution of the resulting dense matrix systems have enabled linear time complexity and memory usage. However, these methods tend to have large disparities between setup and matrix-vector product times that affe... View full abstract»

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  • Accurate and efficient modeling of SOI MOSFET with technology independent neural networks

    Publication Year: 2004, Page(s):1580 - 1587
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    This paper presents neural network (NN) approaches for modeling the I-V characteristics of silicon-on-insulator MOSFETs. The modeling approach is technology independent, fast, and accurate, which makes it suitable for circuit simulators. In the model, two different NN architectures, namely, multilayer perceptron and generalized radial basis function, are used and compared. To increase the training... View full abstract»

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  • Vector-restoration-based static compaction using random initial omission

    Publication Year: 2004, Page(s):1587 - 1592
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a synchronous sequential circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted f... View full abstract»

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  • Compact, netlist-based representation of thermal transient coupling using controlled sources

    Publication Year: 2004, Page(s):1593 - 1596
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    A compact, efficient electrical dual-circuit topology for the representation of transient thermal coupling is presented. Based on controlled sources, the method allows an arbitrary level of complexity to be used for each self and coupled response. Two possible variations on the circuit form, and the resulting requirements for model extraction, are developed. The method is applied to the modeling o... View full abstract»

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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu