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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 11 • Date Nov. 2004

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Guest Editorial

    Publication Year: 2004, Page(s):1129 - 1131
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  • CAD for nanometer silicon design challenges and success

    Publication Year: 2004, Page(s):1132 - 1147
    Cited by:  Papers (20)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1791 KB) | HTML iconHTML

    As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complex... View full abstract»

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  • Impedance characteristics of power distribution grids in nanoscale integrated circuits

    Publication Year: 2004, Page(s):1148 - 1155
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (441 KB) | HTML iconHTML

    The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis dif... View full abstract»

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  • Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

    Publication Year: 2004, Page(s):1156 - 1166
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2643 KB) | HTML iconHTML

    In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a... View full abstract»

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  • Nanoscale system dynamical behaviors: from quantum-dot-based cell to 1-D arrays

    Publication Year: 2004, Page(s):1167 - 1173
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB) | HTML iconHTML

    In this paper, we consider coupled quantum-dot cells, which are usually used for quantum-dot cellular automata, to build nanoscale dynamical systems. In particular, it is shown how the simple connection of few quantum-dot cells, quantum cellular nonlinear networks (Q-CNNs), can cause the onset of chaotic oscillations. Complex dynamics can be obtained only with small differences of polarizations an... View full abstract»

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  • Baud-rate channel equalization in nanometer technologies

    Publication Year: 2004, Page(s):1174 - 1181
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    Chip design technology has been accelerating the advances of the communication technology in the past decades because a chip with larger computing capacity can support a communication system of higher transmission bandwidth. Since the communication transceivers are now in the multigiga bits/second range, the computing bandwidth requirement for a transceiver has grown into several hundreds of giga-... View full abstract»

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  • Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems

    Publication Year: 2004, Page(s):1182 - 1191
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB) | HTML iconHTML

    In this paper, a learnable cellular nonlinear network (CNN) with space-variant templates, ratio memory (RM), and modified Hebbian learning algorithm is proposed and analyzed. By integrating both the modified Hebbian learning algorithm with the self-feedback function and a ratio memory into CNN architecture, the resultant ratio-memory (RMCNN) is called the self-feedback RMCNN (SRMCNN) which can ser... View full abstract»

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  • Interconnect accelerating techniques for sub-100-nm gigascale systems

    Publication Year: 2004, Page(s):1192 - 1200
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current and thus improve the signal transition time. Besides, the capacitor coupling technique is applied to a... View full abstract»

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  • Large-signal two-terminal device model for nanoelectronic circuit analysis

    Publication Year: 2004, Page(s):1201 - 1208
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    As the nanoelectronics field reaches the maturity needed for circuit-level integration, modeling approaches are needed that can capture nonclassical behaviors in a compact manner. This paper proposes a universal device model (UDM) for two-terminal devices that addresses the challenge of correctly balancing accuracy, complexity, and flexibility. The UDM qualitatively captures fundamental classical ... View full abstract»

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  • Analog-to-digital converter based on single-electron tunneling transistors

    Publication Year: 2004, Page(s):1209 - 1213
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB) | HTML iconHTML

    A novel single-electron tunneling transistors (SETTs) based analog-to-digital converter (ADC) is proposed in this paper. The scheme we propose fully utilizes Coulomb oscillation effect, can properly operate at T>0 K, and only a capacitive divider (built with 2n-2 capacitors) and n pairs of complementary SETTs are required for an n-bit ADC implementation. When compared with other state-of-the-art S... View full abstract»

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  • The design of DNA self-assembled computing circuitry

    Publication Year: 2004, Page(s):1214 - 1220
    Cited by:  Papers (20)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1099 KB) | HTML iconHTML

    We present a design methodology for a nanoscale self-assembling fabrication process that uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom design software allows us to specify the function of a structure in a way similar to that used by VLSI circuit designers. In an analogous manner to generating masks for a photolithographic process, our software gen... View full abstract»

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  • Characterization and modeling of run-time techniques for leakage power reduction

    Publication Year: 2004, Page(s):1221 - 1233
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (622 KB) | HTML iconHTML

    While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance pena... View full abstract»

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  • Lowering power consumption in concurrent checkers via input ordering

    Publication Year: 2004, Page(s):1234 - 1243
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB) | HTML iconHTML

    This paper presents an efficient and scalable technique for lowering power consumption in checkers used for concurrent error detection. The basic idea is to exploit the functional symmetry of concurrent checkers with respect to their inputs, and to order the inputs such that switching activity (and hence power consumption) in the checker is minimized. The inputs of the checker are usually driven b... View full abstract»

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  • Multimode power modeling and maximum-likelihood estimation

    Publication Year: 2004, Page(s):1244 - 1248
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    It is known that circuits exhibit multiple modes of power consumption due to various factors such as the presence of many feedback (or sequential) elements, RAM, large size, etc. Previous power-estimation techniques have largely ignored this fact. For example, Monte Carlo simulation-based power estimators tend to produce estimates for the average power consumption that corresponds only to the most... View full abstract»

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  • Ultralow-power adiabatic circuit semi-custom design

    Publication Year: 2004, Page(s):1248 - 1253
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were ... View full abstract»

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  • Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

    Publication Year: 2004, Page(s):1253 - 1257
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    Matching input/output (I/O) driver output resistance to transmission line impedance is critical for high-speed I/O operation in source series termination environments. Tuning driver output resistance can be accomplished through the use of calibration circuitry. Under ideal conditions, calibration circuitry can properly calibrate an I/O driver. Operating in an environment with die process, voltage,... View full abstract»

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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1258
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2004, Page(s): 1259
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004, Page(s): 1260
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu