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Solid-State Circuits, IEEE Journal of

Issue 11 • Date Nov. 2004

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Displaying Results 1 - 25 of 38
  • [Front cover]

    Page(s): c1 - c4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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  • Table of contents

    Page(s): 1797 - 1798
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  • A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

    Page(s): 1799 - 1808
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    A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm2 in 0.35-μm CMOS. View full abstract»

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  • A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS

    Page(s): 1809 - 1818
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    A single-loop third-order switched-capacitor Σ-Δ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 μW under 1-V supply voltage and the chip core size is 0.18 mm2. View full abstract»

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  • A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth

    Page(s): 1819 - 1828
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    This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator (CT-ΔΣM) that can be used in wireless CDMA receivers. The CT-ΔΣM samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The CT-ΔΣM was fabricated in a 0.18-μm 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2. The ΔΣM's critical performance specifications are derived from the CDMA receiver specifications. View full abstract»

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  • A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

    Page(s): 1829 - 1838
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    A dual 10-b/200-MSPS pipelined digital-to-analog converter (DAC) suitable for communication applications is here presented. Prior implementation limitations have been overcome through circuit techniques. A prototype has been designed using a 4-metal-levels 3.3-V 0.5-μm BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay-locked loop (DLL). The DAC shows 9.7 effective bits and 70 dB of spurious free dynamic range for a synthesized sine wave of 2 Vpp at 34 MHz and output rate of 200 MSPS. Altogether, the two DACs, their reference, and the DLL occupy an active area of 2.28 mm2 and consume 693 mW at full speed. View full abstract»

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  • A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

    Page(s): 1839 - 1852
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    An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under ±0.20 LSB and INL less than ±0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time. View full abstract»

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  • A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR

    Page(s): 1853 - 1861
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    This paper describes a coordinate rotation technique for implementing a quadrature digital synthesizer/mixer (QDSM). Utilizing the concept of fine/coarse decomposition, large-sized look-up tables for evaluating sine and cosine functions are avoided. Interpolation-based fine evaluation enables high-precision to be maintained without increasing the size of the tables. A prototype QDSM was implemented on a 0.51-mm2 die area using a 0.25-μm CMOS technology. The prototype IC generates 15-b complex output from both 14-b complex input and an internally synthesized complex carrier with a spurious-free dynamic range (SFDR) greater than 100 dBc. It functions correctly up to 330 MHz, consuming 460 mW. View full abstract»

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  • A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

    Page(s): 1862 - 1872
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    This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply. View full abstract»

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  • A 1-V 5.2-GHz CMOS synthesizer for WLAN applications

    Page(s): 1873 - 1882
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    A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-μm CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm2. View full abstract»

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  • On the phase-noise and phase-error performances of multiphase LC CMOS VCOs

    Page(s): 1883 - 1893
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    This paper presents an analysis of phase noise in multiphase LC oscillators, and measurement results for several CMOS quadrature-voltage-controlled-oscillators (QVCOs) working in the 2-GHz frequency range. The phase noise data for a so-called BS-QVCO (-140 dBc/Hz or less at 3 MHz frequency offset from the carrier, for a power consumption of 20.8 mW and a figure-of-merit of 184 dBc/Hz) show that phase noise performances are close to the previously derived limits. A systematic cause of departure from ideal quadrature between QVCO signals is also analyzed and measured experimentally, and a compact LC-tank layout that removes this source of phase error is proposed. A TS-QVCO designed with this technique shows a phase-noise figure-of-merit improvement of 4 dB, compared to a previous implementation. The measured equivalent phase error for all QVCOs is between 0.6° and 1°. View full abstract»

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  • An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS

    Page(s): 1894 - 1908
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    This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-μm digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin. View full abstract»

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  • An 8-Gb/s capacitively coupled receiver with high common-mode rejection for uncoded data

    Page(s): 1909 - 1915
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    An 8-Gb/s receiver is demonstrated in 0.35-μm SiGe with two on-chip 60-fF ac-coupling capacitors. These capacitors are formed by on-chip metal layers and have a breakdown voltage of at least ±690 V, which is the dc input range of the receiver. The receiver especially resists strong ac common-mode edges with a slew rate up to 4V/ns for enhanced EMI rejection. The self-clocked quantized feedback technique used, features uncoded data that contains long sequences of consecutive identical digits or ac-unbalanced data. The differential input sensitivity is 0.5-1.1Vpp with a supply voltage between 2.5 and 3.5 V. View full abstract»

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  • A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for Bluetooth and 802.11b

    Page(s): 1916 - 1926
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    High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-μm CMOS occupies 4×4 mm2 including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode. View full abstract»

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  • A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

    Page(s): 1927 - 1937
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    A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-μm CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications. View full abstract»

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  • High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

    Page(s): 1938 - 1947
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    A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-μm CMOS technology demonstrates that the circuit draws only 7-μA static current and exhibits the settling times of 2.7 μs for rising and 2.9 μs for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5×57μm2. View full abstract»

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  • A 20-W stereo class-D audio output power stage in 0.6-μm BCDMOS technology

    Page(s): 1948 - 1958
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    This paper presents a highly power efficient 2×20-W class-D audio output power stage implemented in 0.6-μm BCDMOS technology. The presented power stage is capable of driving 2×8-Ω loads from a 20-V power supply at a power efficiency approaching 90%. Circuit details of thermal detection, over-current protection, and startup speaker click/pop are also presented. The performance of open-loop Class-D output stages are limited by the distortion mechanisms present within the power stage itself. A third-order PWM modulator was prototyped and used to dramatically improve the performance of the Class-D output stage by using feedback. The results of this work are also presented. View full abstract»

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  • Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications

    Page(s): 1959 - 1967
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    In this article, the large-signal, small-signal, and noise performance of the Cherry-Hooper amplifier with emitter-follower feedback are analyzed from a design perspective. A method for choosing the component values to obtain a low group delay distortion or Bessel transfer function is given. The design theory is illustrated with an implementation of the circuit in a 47-GHz SiGe process. The amplifier has 19.7-dB gain, 13.7-GHz bandwidth, and ±10-ps group delay distortion. The amplifier core consumes 34 mW from a -3.3-V supply. View full abstract»

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  • A 230-nW 10-s time constant CMOS integrator for an adaptive nerve signal amplifier

    Page(s): 1968 - 1975
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    This paper describes a micropower CMOS integrator with an extremely large time constant for use in a variety of low-frequency signal processing applications. The specific use of the integrator in an implantable biomedical integrated circuit is described. The integrator is based on the OTA-C approach and a very small transconductance of 100 pA/V was achieved by cascading a short chain of transconductance-transimpedance stages. The time constant of the integrator is tunable between about 0.2 and 10 s, and any offset voltages at the output terminal can be trimmed out. The circuit was fabricated in a 0.8-μm CMOS process, dissipates 230 nW from ±1.5 V power supplies (excluding the bias circuitry and output buffers) and has a core area of 0.1 mm2. The integrator offers superior performance in terms of power consumption, die area and time constant when compared to previously published work. View full abstract»

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  • Fully integrated wideband high-current rectifiers for inductively powered devices

    Page(s): 1976 - 1984
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    This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-μm 1M/2P N-epi BiCMOS, and the AMI 1.5-μm 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm2 in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range. View full abstract»

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  • A 10-nW 12-bit accurate analog storage cell with 10-aA leakage

    Page(s): 1985 - 1996
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    Medium-term analog storage offers a compact, accurate, and low-power method of implementing temporary local memory that can be useful in adaptive circuit applications. The performance of these cells is characterized by the sampling accuracy and voltage droop that can be achieved with a given level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized in a standard 1.5-μm CMOS process using an on-chip current integration technique, focusing specifically on the 1 fA to 1 aA current range. These measurements reveal an accumulation-mode source-drain coupling mechanism that can easily dominate diode leakage under certain bias conditions and may have limited previous designs. A simple rule-of-thumb is offered for avoiding this leakage effect, leading to a novel ultra-low leakage switch topology. A differential storage cell incorporating this new switch achieves an average leakage of 10 aA at room temperature, an 8× reduction over past designs. The cell loses one bit of voltage accuracy, 700 μV on a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min, respectively. This represents a 15× increase in hold time at these voltage accuracies over the lowest leakage cell to date, in only 92% of the area. Since the leakage is independent of amplifier bias, the cell can operate on as little as 10 nW of power. Initial measurements also indicate the switch's leakage decreases with the square of process feature size. View full abstract»

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  • A high-resolution synchronous mirror delay using successive approximation register

    Page(s): 1997 - 2004
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    A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-μm 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles. View full abstract»

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  • A dynamic scaling FFT processor for DVB-T applications

    Page(s): 2005 - 2013
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    This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-μm single-poly six-metal CMOS process with core area of 4.84 mm2. Power dissipation is about 25.2 mW at 20 MHz. View full abstract»

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  • Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

    Page(s): 2014 - 2023
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    Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-μm CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm2 and the cell size is 0.121 μm2. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan