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IEEE Transactions on Advanced Packaging

Issue 3 • Aug. 2004

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2004, Page(s): c1
    Cited by:  Papers (1)
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  • IEEE Transactions on Advanced Packaging publication information

    Publication Year: 2004, Page(s): c2
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  • Stacked modular package

    Publication Year: 2004, Page(s):461 - 466
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is... View full abstract»

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  • High-density packaging for mobile terminals

    Publication Year: 2004, Page(s):467 - 475
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1840 KB) | HTML iconHTML

    Personal electronics devices are miniaturized to be more comfortable to carry. This size reduction desire, together with increased functionality, have become drivers, especially for wireless devices. Mobile terminal electronics have set a challenge for packaging and provided the motivation to verify emerging technologies. Chip scale packages (CSP), flip-chip, and passive integration technologies h... View full abstract»

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  • Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

    Publication Year: 2004, Page(s):476 - 489
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4320 KB) | HTML iconHTML

    The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the proces... View full abstract»

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  • A wafer-level microcap array to enable high-yield microsystem packaging

    Publication Year: 2004, Page(s):490 - 496
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB) | HTML iconHTML

    Packaging represents a significant and expensive obstacle in commercializing microsystem technology (MST) devices such as microelectromechanical systems (MEMS), microopticalelectromechanical systems (MOEMS), microsensors, microactuators, and other micromachined devices. This paper describes a novel wafer-level protection method for MSTs which facilitate improved manufacturing throughput and automa... View full abstract»

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  • High-speed interconnects with underlayer orthogonal metal grids

    Publication Year: 2004, Page(s):497 - 507
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB) | HTML iconHTML

    On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of convention... View full abstract»

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  • Materials and processes for implementing high-temperature liquid interconnects

    Publication Year: 2004, Page(s):508 - 514
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3664 KB) | HTML iconHTML

    This paper describes the results of a study investigating liquid solder joints at elevated temperatures (up to 200°C). The reactions of eutectic 52In/48Sn solder, which melts at 118°C, with various metal barrier layers is presented. The main emphasis of the research was to find a combination of solder and substrate metallization which has good adhesion strength but also remains stable duri... View full abstract»

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  • Recent advances in flip-chip underfill: materials, process, and reliability

    Publication Year: 2004, Page(s):515 - 524
    Cited by:  Papers (81)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB) | HTML iconHTML

    In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these... View full abstract»

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  • Novel reworkable fluxing underfill for board-level assembly

    Publication Year: 2004, Page(s):525 - 532
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB) | HTML iconHTML

    Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfill... View full abstract»

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  • Enhancement of underfill capillary flow in flip-chip packaging by means of the inertia effect

    Publication Year: 2004, Page(s):533 - 539
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB) | HTML iconHTML

    This paper describes how the use of inertia forces induced by the rotation of a working disk may be adopted to increase the fill rate of the flip-chip packaging process and thereby reduce the process cycle time. It is shown how the driving forces resulting from the inertia effect are determined by the Weber number. The constant and varying contact angle models are compared under a specified set of... View full abstract»

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  • Via etching through extremely thick organic dielectrics

    Publication Year: 2004, Page(s):540 - 544
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1528 KB) | HTML iconHTML

    A process for etching vias in extremely thick (85 to 152 μm) HD MicroSystems polyimide PI2611 was developed using commercial reactive ion etching tools. Sloped via profiles were obtained using a combination of hard masks made of aluminum and silicon dioxide thin films, combined with reactive ion etch steps in pure O2 and O2/CF4. The deep via profiles provided go... View full abstract»

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  • Thermal assessment of RF-integrated LTCC front end modules

    Publication Year: 2004, Page(s):545 - 557
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2544 KB) | HTML iconHTML

    The thermal performance of front end module (FEM) incorporating low-temperature cofired ceramic (LTCC) substrate is investigated. An infrared microscope system was used to measure device surface temperature with both RF and dc power. Various duty cycles (25% to 100%) were applied to characterize the thermal performance of the device for different power densities. The maximum junction temperature o... View full abstract»

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  • Characterization of an experimental ferrite LTCC tape system for microwave and millimeter-wave applications

    Publication Year: 2004, Page(s):558 - 565
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB) | HTML iconHTML

    An experimental-low temperature cofired ceramic (LTCC) ferrite tape system is characterized using circuits that are fabricated from the very material under test. Such in situ circuits provide data that are thought to be more representative of the performance obtainable by more complicated circuitry that will eventually be made from the same material using the same fabrication method. Emphasis is p... View full abstract»

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  • IEEE Transactions on Electronics Packaging Manufacturing - table of contents

    Publication Year: 2004, Page(s): 566
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  • IEEE Transactions on Components and Packaging Technology - table of contents

    Publication Year: 2004, Page(s):567 - 568
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

    Publication Year: 2004, Page(s): c3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Publication Year: 2004, Page(s): c4
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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering