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Circuits, Devices and Systems, IEE Proceedings -

Issue 4 • Date 12 Aug. 2004

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Displaying Results 1 - 15 of 15
  • Unified matrix method for systematic synthesis of log-domain ladder filters

    Page(s): 285 - 293
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (870 KB)  

    A matrix-based method of synthesising log-domain ladder filters is described. The nodal matrix equations characterising a LCR prototype are made directly realisable, facilitating the design of high-order filters. Different structures with a range of characteristics can be generated by a variety of matrix decompositions. The problem of floating capacitors normally required to realise transmission zeros in the log-domain is solved by matrix transformations. This avoids externally-LTV dynamics and hence distortion. Simulated results of different designs derived by various matrix decompositions validate the proposed procedures, which have been formalised in the CAD filter package XFILTER. View full abstract»

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  • Unified active filter biquad structures

    Page(s): 273 - 277
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (417 KB)  

    The authors present a new biquad filter model based on ators, norators, current mirrors and passive R (resistor) and C (capacitor) elements. Two implementations derived from the new biquad filter model by using second generation current-controlled conveyors (CCCIIs) and operational transconductance amplifiers (OTAs) are also proposed. The two biquad implementations are capable of achieving five important filter performance parameters simultaneously and without trade-offs, including universal filtering, minimum components count and independent control of ωo and ωo/Q. This is unlike recently reported filter structures which make certain trade-offs that emphasise some parameters at the cost of others. Simulation results are included confirming the theoretical prediction. View full abstract»

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  • Modelling and analysis of ground bounce due to internal gate switching

    Page(s): 300 - 306
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    Ground bounce noise due to internal gate switching is studied. Unlike the ground bounce caused by switching of the output buffer, both power-rail and ground-rail impedances are important, and a double negative feedback mechanism must be considered. Based on the lumped-model analysis and taking into account the parasitic and velocity-saturation effects of MOS transistors, an analytical model is developed including both switching and non-switching gates. The proposed model is employed to analyse the on-chip decoupling capacitance, resonant frequency, wire/pin inductance and loading effect. Good agreement between the model predictions and SPICE simulation results is obtained. View full abstract»

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  • TOP: an algorithm for three-level combinational logic optimisation

    Page(s): 307 - 314
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type gg2, where g1 and g2 are sum-of-products expressions and '°' is a binary operation. For the first time, to the authors' knowledge, this problem is addressed for an arbitrary operation '°', although several algorithms for specified cases of '°' have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser. View full abstract»

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  • Energy-efficient self-timed circuit design using supply voltage scaling

    Page(s): 278 - 284
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (627 KB)  

    Energy-efficient design for self-timed circuits is investigated. Null convention logic is employed to construct speed-independent self-timed circuits. For error-free computation, the supply voltage automatically tracks the input data rate so that the supply voltage can be kept as small as possible while maintaining the speed requirement. For error-tolerable computation, such as soft digital signal processing, further energy saving is achieved at the cost of signal-to-noise ratio when an ultralow supply voltage is applied. Cadence simulation shows that 40 to 70% power can be saved by introducing -15 to -11 dB error in typical speech signal processing. View full abstract»

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  • Contact modelling of heterojunction acoustic transport devices

    Page(s): 322 - 325
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A method is presented for contact modelling of heterojunction acoustic charge transport devices (HACT). The method is used to optimise the ohmic contact dimensions, especially contact depths. It uses a solution of the two-dimensional Poisson equation, the continuity equations for electrons and holes, the current densities, the displacement charges resulting from the acoustic wave as well surface state densities. This solution gives the potential and charge distribution in the charge injection region of HACT devices for different depths of ohmic contacts. The channel current densities are computed as a function of gate applied voltages. This technique is developed to calculate the I-V characteristics; then the most suitable choice of the ohmic contact depth taking into account these I-V characteristics is given. This method is applied to calculate the optimal depth of ohmic contacts in the case of a conventional HACT (n-HACT). This result will be very useful for HACT structure design. View full abstract»

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  • Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers

    Page(s): 337 - 348
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (485 KB)  

    Charge-pump phase-locked loops (CP-PLL) are the circuit architecture of choice for embedded frequency synthesis applications. In all situations a frequency synthesis system will generate timing or reference signals for other important system functions. Therefore, it is a key element for satisfactory system level operation and must be verified correctly. The key performance metric for CP-PLLs is often stated in terms of spectral purity or jitter of the generated output signal. However, in a production test environment it can be difficult to assess system performance directly in these terms. For a correctly designed system, output signal degradation can often be related back to deviations or errors introduced during the manufacturing process. In many instances the CP-PLL may be the only analogue block present on a digital SoC (system on chip), and in consequence production test is often focused towards sufficient verification using methods applicable for digital only testers. Direct access DfT (design for test) techniques are often employed to address test requirements for analogue portions of the CP-PLL; however, problems can occur in terms of noise injection and general test access. The paper presents an introductory overview and tutorial providing information relating to key CP-PLL deviations, common direct access DfT extraction methods and the associated problems. In addition, a review of recent significant BIST (built-in-self-test)/DfT test approaches is provided. The focus is on methods that can indirectly validate CP-PLL closed loop performance and be useful in highlighting key jitter or phase noise contributors. View full abstract»

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  • SiGe HBT serial transmitter architecture for high speed variable bit rate intercomputer networking

    Page(s): 315 - 321
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1319 KB)  

    A monolithic transmitter architecture that addresses difficulties in data retiming at high bit rates has been designed and fabricated. It utilises a quarter-frequency multiplexing scheme, a fully symmetric multiplexer and a feedforward interpolated ring voltage controlled oscillator (VCO), to transmit data in excess of 20 Gbit/s. The symmetric multiplexer has full input and output symmetry designed to have the same delay from any input to the output. Each stage in the VCO controls its delay by linearly interpolating the signals from the previous two stages, yielding a VCO tuning range of 3.7 to 5.5 GHz with a phase noise of -90.2 dBc/Hz at 1 MHz. SiGe heterojunction bipolar technology (HBT) technology with an fT of 50 GHz was used in this design. View full abstract»

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  • Digital test for the extraction of integrator leakage in first- and second-order ΣΔ modulators

    Page(s): 349 - 358
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (353 KB)  

    A digital technique for evaluating the integrator leakage within first- and second-order ΣΔ modulators is proposed. It involves a very small amount of hardware, which makes it specially suitable for built-in self-test (BIST) implementation. Integrator leakage is known to be related to the converter precision and, hence, the proposed test technique serves as an indirect test of the signal-to-noise ratio (SNR) degradation. As an additional result, a strategy has been derived for digitally correcting the SNR loss due to integrator leakage in cascaded modulators. View full abstract»

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  • Robust technique for on-chip DC current measurements

    Page(s): 371 - 378
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (518 KB)  

    A robust and highly scalable technique for measuring DC currents is described. The circuit consists largely of digital electronics except for a comparator and a passive RC filter. This simple structure is able to force a voltage at a circuit node while measuring the current that flows into it. The technique has been successfully demonstrated using a prototype constructed using a 0.35 μm CMOS chip. View full abstract»

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  • Analytical input mapping for modelling energy dissipation of complex CMOS gates

    Page(s): 294 - 299
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    Input mapping is an important step used in the equivalent inverter modelling technique to estimate energy dissipation in CMOS gates. The purpose of the input mapping is to map multiple inputs of a gate into one equivalent input to simplify the analysis process. An analytical input mapping method for all possible inputs of parallel circuit structures is presented. An application of the equivalent inverter modelling technique using this algorithm on complex CMOS gates containing feedback structures is also included. The model is verified by Cadence SPICE simulation. Very good agreement between the model predictions and simulation results is obtained. View full abstract»

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  • Conductive polymer gate FET devices for vapour sensing

    Page(s): 326 - 334
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (715 KB)  

    The development of ultra low-power CMOS compatible gas sensors has been the goal of many research groups for a number of years. Such sensors benefit from both a low fabrication cost and an ease of integration with any associated transducer or signal processing circuitry. A sensor with these attributes is proposed comprising a novel chemFET sensor, with a conducting polymer gate, that operates at ambient temperature. Both electrochemically deposited and polymer composite materials have been deposited to form the gate electrode of an n-channel enhanced MOSFET (ECFET and PCFET, respectively). The authors present the first full characterisation of these sensors in terms of their response to pulses of ethanol and toluene vapour in air. In addition, environmental effects of temperature and humidity on both the baseline signal (i.e. zero vapour) and vapour response have been investigated. The PCFET and ECFET vapour sensitivities (operating at constant current) were found to be up to 5.5 μV/ppm and -2.3 μV/ppm for toluene and 0.6 μV/ppm and 4.5 μV/ppm for ethanol, respectively. The relative selectivity of the chemFET sensors was observed to be up to 564 for these two organics, with an observed sign change with certain polymers. In addition, the detection limits have been estimated to be below 1 ppm of toluene and ethanol vapour in air. It was also found that increasing temperature resulted in a reduction in both baseline and response signals, which the authors postulate is due to a reduction in the bulk solubility of the polymer. The authors believe that the low power of operation, range of polymers and integration with standard electronics makes these sensors ideal for a new range of hand-held electronic noses. View full abstract»

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  • Flexible embedded test solution for high-speed analogue front-end architectures

    Page(s): 359 - 369
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    A flexible embedded test solution for high-speed analogue front-end subsystems is presented. A novel concept of a flexible test solution that addresses virtual component test requirements in particular is introduced. The integration and application of the non-invasive digital test solution is demonstrated for a representative design. Its area overhead is assessed for different depths in on-chip test evaluation. View full abstract»

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  • Wavelet neural network approach for fault diagnosis of analogue circuits

    Page(s): 379 - 384
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (295 KB)  

    A systematic method for fault diagnosis of analogue circuits based on the combination of neural networks and wavelet transforms is presented. Using wavelet decomposition as a tool for removing noise from the sampled signals, optimal feature information is extracted by wavelet noise removal, multi-resolution decomposition, PCA (principal component analysis) and data normalisation. The features are applied to the proposed wavelet neural network and the fault patterns are classified. Diagnosis principles and procedures are described. The reliability of the method and comparison with other methods are shown by two active filter examples. View full abstract»

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  • Analogue and mixed-signal test for systems on chip

    Page(s): 335 - 336
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (207 KB)  

    Reports some advances in the research of DFT, BIST, digital test methods, on-chip test and robust diagnosis of analogue and mixed-signal circuits. Analogue and mixed-signal components most widely used in SoCs are all covered, including filters, amplifiers, data converters, ΣΔ-modulators, phase-locked loops and frequency synthesisers. View full abstract»

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