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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2004

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Displaying Results 1 - 25 of 39
  • Table of contents

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Impact of compositionally graded base regions on the DC and RF properties of reduced turn-on voltage InGaP-GaInAsN DHBTs

    Page(s): 1545 - 1553
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    Built-in drift fields are employed to enhance the performance of GaAs-based heterojunction bipolar transistors (HBTs) with reduced turn-on voltage. Specifically, we explore in detail the dc and RF device property improvements enabled by using compositionally graded GaInAsN base layers. Experimental results are compared to predictions of the standard drift-diffusion base transport model employing a finite exit velocity. In large area devices, graded base samples with built-in fields of ∼7 kV/cm (i.e. 40 meV over 500 Å) typically have a dc current gain 1.8× larger than constant base composition samples. In small area devices, the peak cut-off frequency is typically 10%-15% higher than constant composition samples. These results are shown to agree reasonably well with predictions, thereby demonstrating that analytical drift-diffusion based models can be extended to HBTs with GaInAsN base layers. View full abstract»

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  • Surface-related drain current dispersion effects in AlGaN-GaN HEMTs

    Page(s): 1554 - 1561
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    Drain current dispersion effects are investigated in AlGaN-GaN HEMTs by means of pulsed, transient, and small-signal measurements. Gate- and drain-lag effects characterized by time constants in the order of 10-5-10-4 s cause dispersion between dc and pulsed output characteristics when the gate or the drain voltage are pulsed. An activation energy of 0.3 eV is extracted from temperature-dependent gate-lag measurements. We show that two-dimensional numerical device simulations accounting only for polarization charges and donor-like traps at the ungated AlGaN surface can quantitatively reproduce all dispersion effects observed experimentally in the different pulsing modes, provided that the measured activation energy is adopted as the energetic distance of surface traps from the valence-band edge. Within this hypothesis, simulations show that surface traps behave as hole traps during transients, interacting with holes attracted at the AlGaN surface by the negative polarization charge. View full abstract»

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  • Opto-electronic properties of poly (fluorene) co-polymer red light-emitting devices on flexible plastic substrate

    Page(s): 1562 - 1569
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    In this paper, we report on the multilayer poly (fluorene) co-polymer red light-emitting devices (PLEDs) fabricated on flexible plastic substrates. An organic hole transport layer (HTL) is inserted between PEDOT:PSS hole injection (HIL) and light-emissive layers (LEL). Since the highest occupied molecular orbital (HOMO) of the HTL is located between those of HIL and LEL, the insertion of HTL reduces the effective HOMO level offset between HIL and LEL, reducing the device operation voltage and producing comparable or better device efficiencies in comparison with the conventional PEDOT:PSS-only devices. Maximum emission efficiency, ∼0.8 cd/A, power efficiency, ∼0.7 lm/W, and external quantum efficiency, ∼1.5%, have been obtained for multilayer red PLEDs. View full abstract»

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  • Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

    Page(s): 1570 - 1576
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    This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified. View full abstract»

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  • Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

    Page(s): 1577 - 1583
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    A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the dishing radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations. View full abstract»

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  • Successive oxide breakdown statistics: correlation effects, reliability methodologies, and their limits

    Page(s): 1584 - 1592
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    This paper deals with the statistics of successive oxide breakdown (BD) events in MOS devices. Correlation effects between these successive events are experimentally related to the statistics of BD current jumps, thus suggesting that they are related to lateral propagation of the BD path. The application of the successive BD theory to chip reliability assessment is discussed. Several failure criteria and the related reliability methodologies are considered and some of their limits are established. View full abstract»

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  • On the physical mechanism of the NROM memory erase

    Page(s): 1593 - 1599
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    The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed. View full abstract»

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  • On the threshold Voltage of symmetrical DG MOS capacitor with intrinsic silicon body

    Page(s): 1600 - 1604
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    An analytical expression explicitly relating the potential and the electric field at the oxide-semiconductor interface of a symmetrical double-gate oxide-intrinsic semiconductor-oxide system is derived. The expression is continuously applicable to all regimes of operation. The "turn-on" behavior of the system is studied and an "extrapolated" threshold voltage is uniquely defined. Opposite to the behavior of a conventional bulk metal-oxide-semiconductor capacitor realized on a doped substrate, this threshold voltage is shown to decrease with increasing oxide thickness. View full abstract»

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  • Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs

    Page(s): 1605 - 1612
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    Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (fmax) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs. View full abstract»

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  • Erratic cell behavior in channel hot electron programming of NOR flash memories

    Page(s): 1613 - 1620
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  • CMOS circuit performance enhancement by surface orientation optimization

    Page(s): 1621 - 1627
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    With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-κ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-κ interface. Additional concerns including layout area and device reliability are discussed. View full abstract»

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  • On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

    Page(s): 1628 - 1635
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    A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-μm salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit. View full abstract»

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  • Statistical simulations for flash memory reliability analysis and prediction

    Page(s): 1636 - 1643
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    In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (VT) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements. View full abstract»

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  • A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon

    Page(s): 1644 - 1652
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    Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p+ poly gate formed by BF2 ion implanted compensation of in situ phosphorus (n+) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n+- and p+-doped WSix-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-κ Al2O3 and HfO2 dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability. View full abstract»

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  • Accurate evaluation of mobility in high gate-leakage-current MOSFETs by using a transmission-line model

    Page(s): 1653 - 1658
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    The effect of high gate-leakage current on the accuracy of mobility evaluation was investigated. This investigation showed that a high gate leakage current makes it difficult to measure the mobility accurately in the case of using a conventional equivalent circuit with lumped circuit elements. To measure the mobility accurately, the authors therefore used a transmission-line model. Its validity was experimentally confirmed by using the capacitance-frequency characteristic of the gate of MOSFETs. The transmission-line model shows that a high gate-leakage current induces a voltage distribution in the channel, which causes a serious error in the mobility evaluation. Accordingly, a precision parameter, which clarifies the relation between channel length and measurement error, was defined. This parameter was then used to define a criterion for channel length for accurately measuring mobility. The channel-length criterion was used to successfully evaluate the mobility of n-MOSFETs with gate dielectrics of 1.4-nm-thick oxynitride (SiON). View full abstract»

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  • Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

    Page(s): 1659 - 1666
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    An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating. View full abstract»

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  • Shrinkable triple self-aligned field-enhanced split-gate flash memory

    Page(s): 1667 - 1671
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    This paper demonstrates a shrinkable triple self-aligned split-gate flash cell fabricated using a standard 0.13-μm copper interconnect process. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All the processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 μm. It is comparable in area with a stacked-gate cell and can be less than 13F2. The cell is erased by using poly-poly Fowler-Nordheim tunneling with a sharp floating-gate edge to increase the electric field, and is programmed by source-side injection. As a result, this cell is highly suitable for low power applications and embedded products. Characterization shows considerable program and erase speed, up to 300 K times cycling endurance, and excellent disturb margins. View full abstract»

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  • Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling

    Page(s): 1672 - 1678
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    The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 μm. View full abstract»

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  • Low-frequency noise in submicrometer MOSFETs with HfO2, HfO2/Al2O3 and HfAlOx gate stacks

    Page(s): 1679 - 1687
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    Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO2, HfAlOx and HfO2/Al2O3 as the gate dielectric materials. The gate length varied from 0.135 to 0.36 μm with 10.02 μm gate width. The equivalent oxide thicknesses were: HfO2 23 Å, HfAlOx 28.5 Å and HfO2/Al2O3 33 Å. In addition to the core structures with only about 10 Å of oxide between the high-κ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 Å was grown between the high-κ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10-12A(2-5×10-5 A/cm2) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO2 devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8×1017 cm-3eV-1 to 1.3×1019 cm-3eV-1, somewhat higher compared to conventional SiO2 MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-κ/gate stacks, relative comparison among them and to the Si--SiO2 system. View full abstract»

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  • Effects of high electric fields and temperature on conductivity of a-Si

    Page(s): 1688 - 1694
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    At high electric fields the Poole-Frenkel effect and thermally-assisted tunneling give rise to an enhanced electric conductivity of amorphous silicon (a-Si). The occupancy of states in the gap, free, and trapped charge carrier concentrations and electric conductivity of a homogenous a-Si in steady-state conditions are calculated on the basis of space-charge neutrality and with time-unchangeable concentrations of charge carriers. Simplifying approximations are introduced, thus enabling easier calculations of carrier concentrations and conductivity. The theory of capture-emission dynamics in a-Si at high fields is further extended by expressing occupancy functions and nonequilibrium quasi-Fermi levels. Effects of the density of states distribution in a-Si and added impurities upon carrier concentrations and conductivity are revealed. View full abstract»

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  • Moving current filaments in integrated DMOS transistors under short-duration current stress

    Page(s): 1695 - 1703
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    Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges. View full abstract»

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  • Hot hole degradation effects in lateral nDMOS transistors

    Page(s): 1704 - 1710
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    The degradation of a n-type lateral DMOS transistor is shown to be related to the injection of hot holes in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. The dependency of the hot hole injection on the layout of the LDMOS transistors is studied. View full abstract»

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  • Investigations on the high current behavior of lateral diffused high-voltage transistors

    Page(s): 1711 - 1720
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    This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego