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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct. 2004

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Network flow techniques for dynamic voltage scaling in hard real-time systems

    Publication Year: 2004, Page(s):1385 - 1398
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB) | HTML iconHTML

    Energy consumption is an important performance parameter for portable and wireless embedded systems. However, energy consumption must be carefully balanced with real-time responsiveness in hard real-time systems. In this paper, we present two offline dynamic voltage scaling (DVS) schemes for dynamic power management in such systems. In the first method, we develop a generalized network flow (GNF) ... View full abstract»

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  • MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation

    Publication Year: 2004, Page(s):1399 - 1410
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB) | HTML iconHTML

    In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias. The device current is described by two main equations handling the MOS channel and the drift region, both of which are smooth and continuous in all operating regi... View full abstract»

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  • A circuit-compatible model of ballistic carbon nanotube field-effect transistors

    Publication Year: 2004, Page(s):1411 - 1420
    Cited by:  Papers (109)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit... View full abstract»

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  • ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

    Publication Year: 2004, Page(s):1421 - 1428
    Cited by:  Papers (8)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB) | HTML iconHTML

    On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verifica... View full abstract»

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  • Multiphase BIST: a new reseeding technique for high test-data compression

    Publication Year: 2004, Page(s):1429 - 1446
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB) | HTML iconHTML

    In this paper, a new reseeding architecture for scan-based built-in self-test (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation... View full abstract»

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  • Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip

    Publication Year: 2004, Page(s):1447 - 1459
    Cited by:  Papers (9)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB) | HTML iconHTML

    We present a new partition-based fault-diagnosis technique for identifying error-capturing scan cells in a scan-BIST environment. This approach relies on a two-step scan chain partitioning scheme. In the first step, an interval-based partitioning scheme is used to generate a small number of partitions, where each element of a partition consists of a set of consecutive scan cells. In the second ste... View full abstract»

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  • Noise-rejection model based on charge-transfer equation for digital CMOS circuits

    Publication Year: 2004, Page(s):1460 - 1468
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Noise-rejection curve (NRC) is given by minimum noise amplitude that causes failure of digital cell as a function of noise width. It is more accurate noise failure criteria than traditional static noise margin (NM) and it becomes widely used in modern crosstalk aware designs. However, the accuracy of the NRC-based analysis is often insufficient because of inconsistencies between characterization, ... View full abstract»

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  • Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains

    Publication Year: 2004, Page(s):1465 - 1478
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    For a scan design with multiple scan chains, we say that a scan chain is P-testable if it is possible to achieve complete fault coverage for the circuit (i.e., detect all the detectable target faults) when the scan chain is driven from a source that produces values having a property P. For example, a scan chain is random-testable if it is possible to achieve complete fault coverage for the circuit... View full abstract»

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  • Fault secure datapath synthesis using hybrid time and hardware redundancy

    Publication Year: 2004, Page(s):1476 - 1485
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependenc... View full abstract»

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  • A high-efficiency strongly self-checking asynchronous datapath

    Publication Year: 2004, Page(s):1484 - 1494
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and... View full abstract»

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  • Simple model of metal oxide varistor for Pspice Simulation

    Publication Year: 2004, Page(s):1491 - 1494
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Metal oxide varistors (MOVs) are commonly used to suppress transients in many applications, such as industrial process measurement and control instrumentation, when exposed to electromagnetic interference. Varistors symmetrical, sharp breakdown characteristics enable them to provide transient suppression performance. A simple model of MOVs for Pspice simulation is proposed in this paper. The compa... View full abstract»

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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1495
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    Publication Year: 2004, Page(s): 1496
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu