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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 10 • Date Oct. 2004

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Table of contents

IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Editorial

Individual wire-length prediction with application to timing-driven placement

Power estimation techniques for FPGAs

Sequential delay budgeting with interconnect prediction

Design of FPGA interconnect for multilevel metallization

Unifying mesh- and tree-based programmable interconnect

Empirical models for net-length probability distribution and applications

Error-correction and crosstalk avoidance in DSM busses

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

Evaluation of energy consumption in RC ladder circuits driven by a ramp input

Assessment of on-chip wire-length distribution models

Highly efficient, limited range multipliers for LUT-based FPGA architectures

Ant colony system application to macrocell overlap removal

Effects of speculation on performance and issue queue design

Correction to “A Digitally Programmable Delay Element: Design and Analysis”

2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

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