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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 10 • Oct. 2004

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  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Editorial

    Publication Year: 2004, Page(s):1001 - 1003
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  • Individual wire-length prediction with application to timing-driven placement

    Publication Year: 2004, Page(s):1004 - 1014
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (574 KB) | HTML iconHTML

    In this paper, we address the problem of individual wire-length prediction and demonstrate its usefulness in timing-driven placement. Many researchers have observed that different placement algorithms produce different individual wire lengths. We postulate that to obtain accurate results, individual wire-length prediction should be coupled with the placement flow. We embed the wire-length predicti... View full abstract»

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  • Power estimation techniques for FPGAs

    Publication Year: 2004, Page(s):1015 - 1027
    Cited by:  Papers (57)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (733 KB) | HTML iconHTML

    The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power esti... View full abstract»

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  • Sequential delay budgeting with interconnect prediction

    Publication Year: 2004, Page(s):1028 - 1037
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new linear programming for... View full abstract»

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  • Design of FPGA interconnect for multilevel metallization

    Publication Year: 2004, Page(s):1038 - 1050
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1743 KB) | HTML iconHTML

    How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topolo... View full abstract»

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  • Unifying mesh- and tree-based programmable interconnect

    Publication Year: 2004, Page(s):1051 - 1065
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1404 KB) | HTML iconHTML

    We examine the traditional, symmetric, Manhattan mesh design for field-programmable gate-array (FPGA) routing along with tree-of-meshes (ToM) and mesh-of-trees (MoT) based designs. All three networks can provide general routing for limited bisection designs (Rent's rule with p<1) and allow locality exploitation. They differ in their detailed topology and use of hierarchy. We show that all three ha... View full abstract»

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  • Empirical models for net-length probability distribution and applications

    Publication Year: 2004, Page(s):1066 - 1075
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    In this paper, we propose a novel, empirical, and parameterizable model for estimating the probability distribution of wire length for each net in a placed netlist. The model is simple and fast to compute. We did extensive experimentation with state-of-the-art commercial (Cadence) and academic (Parquet and Labyrinth) tools and validated our model. Our distribution model was around three times more... View full abstract»

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  • Error-correction and crosstalk avoidance in DSM busses

    Publication Year: 2004, Page(s):1076 - 1080
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on long, adjacent bus wires can lead to timing violations and logic faults. At the same time, system-level interconnects have also become more susceptible to other less predictable forms of interference such as noise induced by power grid fluctuations, electromagnetic interf... View full abstract»

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  • Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

    Publication Year: 2004, Page(s):1081 - 1093
    Cited by:  Papers (62)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB) | HTML iconHTML

    A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show ... View full abstract»

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  • Evaluation of energy consumption in RC ladder circuits driven by a ramp input

    Publication Year: 2004, Page(s):1094 - 1107
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptot... View full abstract»

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  • Assessment of on-chip wire-length distribution models

    Publication Year: 2004, Page(s):1108 - 1112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of R... View full abstract»

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  • Highly efficient, limited range multipliers for LUT-based FPGA architectures

    Publication Year: 2004, Page(s):1113 - 1118
    Cited by:  Papers (13)  |  Patents (1)
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  • Ant colony system application to macrocell overlap removal

    Publication Year: 2004, Page(s):1118 - 1123
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    We present a novel macrocell overlap removal algorithm, based on the ant colony optimization metaheuristic. The procedure generates a feasible placement from a relative placement with overlaps produced by some placement algorithms such as quadratic programming and force-directed. It uses the concept of ant colonies, a set of agents that work together to improve an existing solution. Each ant in th... View full abstract»

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  • Effects of speculation on performance and issue queue design

    Publication Year: 2004, Page(s):1123 - 1126
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB) | HTML iconHTML

    Current trends in microprocessor designs indicate increasing pipeline depth in order to keep up with higher clock frequencies and increased architectural complexity. Speculatively issued instructions are particularly sensitive to increases in pipeline depth. In this brief, we use load hit speculation as an example, and evaluate its cost effectiveness as pipeline depth increases. Our results indica... View full abstract»

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  • Correction to &#8220;A Digitally Programmable Delay Element: Design and Analysis&#8221;

    Publication Year: 2004, Page(s): 1126
    Cited by:  Papers (1)
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1127
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    Publication Year: 2004, Page(s): 1128
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu