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IEEE Transactions on Computers

Issue 11 • Date Nov. 2004

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2004, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2004, Page(s): c2
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  • Guest Editors’ Introduction: Field Programmable Logic and Applications

    Publication Year: 2004, Page(s):1361 - 1362
    Cited by:  Papers (1)
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  • The MOLEN polymorphic processor

    Publication Year: 2004, Page(s):1363 - 1375
    Cited by:  Papers (176)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB) | HTML iconHTML

    In this paper, we present a polymorphic processor paradigm incorporating both general-purpose and custom computing processing. The proposal incorporates an arbitrary number of programmable units, exposes the hardware to the programmers/designers, and allows them to modify and extend the processor functionality at will. To achieve the previously stated attributes, we present a new programming parad... View full abstract»

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  • An asynchronous dataflow FPGA architecture

    Publication Year: 2004, Page(s):1376 - 1392
    Cited by:  Papers (68)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2314 KB) | HTML iconHTML Multimedia Media

    We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high ... View full abstract»

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  • Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

    Publication Year: 2004, Page(s):1393 - 1407
    Cited by:  Papers (134)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB) | HTML iconHTML

    Today's reconfigurable hardware devices have huge densities and are partially reconfigurable, allowing for the configuration and execution of hardware tasks in a true multitasking manner. This makes reconfigurable platforms an ideal target for many modern embedded systems that combine high computation demands with dynamic task sets. A rather new line of research is engaged in the construction of o... View full abstract»

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  • Exploiting program branch probabilities in hardware compilation

    Publication Year: 2004, Page(s):1408 - 1419
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1448 KB) | HTML iconHTML

    This paper explores using information about program branch probabilities to optimize the results of hardware compilation. The basic premise is to promote utilization by dedicating more resources to branches which execute more frequently. A new hardware compilation and flow control scheme are presented which enable the computation rate of different branches to be matched to the observed branch prob... View full abstract»

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  • Performance and area modeling of complete FPGA designs in the presence of loop transformations

    Publication Year: 2004, Page(s):1420 - 1435
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1536 KB) | HTML iconHTML

    Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the Impact and interaction of the transformations. In this paper, we present a combined analytical performance and area mode... View full abstract»

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  • Implementing an OFDM receiver on the RaPiD reconfigurable architecture

    Publication Year: 2004, Page(s):1436 - 1448
    Cited by:  Papers (48)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1352 KB) | HTML iconHTML

    Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications... View full abstract»

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  • Reconfigurable hardware SAT solvers: a survey of systems

    Publication Year: 2004, Page(s):1449 - 1461
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1208 KB) | HTML iconHTML

    By adapting to computations that are not so well-supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application. A great deal of the research effort in this area is aimed at accelerating t... View full abstract»

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  • Schedulability analysis of periodic fixed priority systems

    Publication Year: 2004, Page(s):1462 - 1473
    Cited by:  Papers (68)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    Feasibility analysis of fixed priority systems has been widely studied in the real-time literature and several acceptance tests have been proposed to guarantee a set of periodic tasks. They can be divided in two main classes: polynomial time tests and exact tests. Polynomial time tests can efficiently be used for online guarantee of real-time applications, where tasks are activated at runtime. The... View full abstract»

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  • Parallel cryptographic arithmetic using a redundant Montgomery representation

    Publication Year: 2004, Page(s):1474 - 1482
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB) | HTML iconHTML

    We describe how using a redundant Montgomery representation allows for high-performance SIMD-based implementations of RSA and elliptic curve cryptography. This is in addition to the known benefits of immunity from timing attacks afforded by the use of such a representation. We present some preliminary implementation timings using the SSE2 instruction set on a Pentium 4 processor and show that an S... View full abstract»

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  • Efficient design diversity estimation for combinational circuits

    Publication Year: 2004, Page(s):1483 - 1492
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (815 KB) | HTML iconHTML Multimedia Media

    Redundant systems are designed using multiple copies of the same resource (e.g., a logic network or a software module) in order to increase system dependability: Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations of the same logic function. In a recent ... View full abstract»

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  • Cryptanalysis of a partially known cellular automata cryptosystem

    Publication Year: 2004, Page(s):1493 - 1497
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB) | HTML iconHTML

    Cellular automata provide simple discrete deterministic mathematical models for physical, biological, and computational systems. Despite their simple construction, cellular automata are shown to be capable of complicated behavior and to generate complex and random patterns. There have been constant efforts to exploit cellular automata for cryptography since the very beginning of the research on ce... View full abstract»

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  • A measure of quality for n-detection test sets

    Publication Year: 2004, Page(s):1497 - 1503
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB) | HTML iconHTML

    N-detection test sets are useful in improving the coverage of unmodeled faults. We introduce a measure of quality that allows us to compare two test sets in terms of their ability to detect unmodeled faults based on the concept of n-detections. Using this measure, we describe a procedure for ordering an n-detection test set for stuck-at faults such that the quality of a test set comprised of the f... View full abstract»

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  • Call for Papers for Special Section on Fault Diagnosis and Tolerance in Cryptography

    Publication Year: 2004, Page(s): 1504
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  • TC Information for authors

    Publication Year: 2004, Page(s): c3
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  • [Back cover]

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org