System Maintenance Notice:
Single article purchases and IEEE account management are currently unavailable. We apologize for the inconvenience.
By Topic

Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 2004

Filter Results

Displaying Results 1 - 25 of 32
  • [Front cover]

    Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (105 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Advanced Packaging publication information

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): 237 - 238
    Save to Project icon | Request Permissions | PDF file iconPDF (46 KB)  
    Freely Available from IEEE
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade

    Page(s): 241 - 249
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring- as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

    Page(s): 250 - 267
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1536 KB)  

    From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical- test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stackable system-on-packages with integrated components

    Page(s): 268 - 277
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and development of optoelectronic mixed signal system-on-package (SOP)

    Page(s): 278 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    This paper describes the design and development of a 2.5-Gb/s optical transceiver module as a mixed signal SOP for access networks. The module development consists of concurrent design of an optoelectronic package optimizing optical, electrical, thermal, mechanical functions and optical subassembly and RFICs housed in a chip-on-board package. The optical subassembly (OSA) consists of laser and photodiode assembled on a silicon substrate. The transmit and the receiver sections are combined into a single fiber through a polymer coupler on silicon. The splitter between the transmit and receive section is realized using a polymer waveguide. The electronic ICs are assembled on a multilayer organic substrate. The package design includes optical coupling design, impedance matched transmission line design for RF signals, electrical layout design for mixed signals and thermal design for the package. The module is housed in a plastic molded nonhermetic package to achieve low cost packaging. The assembly is completed using passive alignment of optical devices and attachment of electronic devices using adhesives. In this paper, we present the details of the component design and the development of packaging process methods to achieve the design specifications, test results and process guidelines for assembly and integration. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power distribution networks for system-on-package: status and challenges

    Page(s): 286 - 300
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (976 KB) |  | HTML iconHTML  

    The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Future microprocessors and off-chip SOP interconnect

    Page(s): 301 - 303
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (91 KB) |  | HTML iconHTML  

    Limits to chip power dissipation and power density and limits on the benefits of hyperpipelining in microprocessors threaten to stop the exponential performance growth in microprocessor performance that we have grown accustomed to. Multicore processors can continue to provide historical performance growth on most modern consumer and business applications. However, power efficiency of these cores must also be improved to stay within reasonable power budgets. This can be achieved by simplifying the processor core architecture, and reversing the trend toward ever more-complex and less power-efficient cores. To maintain overall performance growth with stunted per-core and per-thread performance, growth rates will require an even more rapid increase in the number of cores per die. Growing performance by increasing the number of cores on a die at this rate, however, puts unprecedented requirements on the corresponding growth of off-chip bandwidth. We argue that contrary to the international roadmap for semiconductors (ITRS) predictions, off-chip signaling frequencies are likely to exceed the frequencies of processor cores in the not too distant future, consistent with the system-on-package (SOP) concept in the first paper of this issue. If this approach is followed, a 1-TFlops multiprocessor die with 1 TB/s of off-chip bandwidth is feasible at reasonable cost before the end of the decade. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electromagnetic interference (EMI) of system-on-package (SOP)

    Page(s): 304 - 314
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB) |  | HTML iconHTML  

    Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Next-generation microvia and global wiring technologies for SOP

    Page(s): 315 - 325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB)  

    As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-μm area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 μm diameter and lines and spaces of 25 μm. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for micro via wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 μm and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Embedded resistors and capacitors for organic-based SOP

    Page(s): 326 - 331
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3-D-integrated RF and millimeter-wave functions and modules using liquid crystal polymer (LCP) system-on-package technology

    Page(s): 332 - 340
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    Electronics packaging evolution involves system, technology, and material considerations. In this paper, we present a novel three-dimensional (3-D) integration approach for system-on-package (SOP)-based solutions for wireless communication applications. This concept is proposed for the 3-D integration of RF and millimeter (mm) wave embedded functions in front-end modules by means of stacking substrates using liquid crystal polymer (LCP) multilayer and μBGA technologies. Characterization and modeling of high-Q RF inductors using LCP is described. A single-input-single-output (SISO) dual-band filter operating at ISM 2.4-2.5 GHz and UNII 5.15-5.85 GHz frequency bands, two dual-polarization 2×1 antenna arrays operating at 14 and 35 GHz, and a WLAN IEEE 802.11a-compliant compact module (volume of 75×35×0.2 mm3) have been fabricated on LCP substrate, showing the great potential of the SOP approach for 3-D-integrated RF and mm wave functions and modules. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SOP integration and codesign of antennas

    Page(s): 341 - 351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    The successful deployment of wireless systems requires the integration of small, cost-effective antennas while preserving a reasonable electrical performance in the required bandwidth. This paper begins with a short overview of the most important antenna characteristics, and then uses these to describe the minimum requirements and fundamental performance-size limits for electrically small integrated antennas. The performance-size tradeoff is further illustrated by the design of a planar integrated antenna for WLAN. Codesign guidelines are given to avoid parasitic coupling between the integrated antenna and RF circuits. A concluding comparison is made between on-chip and on-package integration of a small antenna for microwave and millimeter wave systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs

    Page(s): 352 - 363
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB) |  | HTML iconHTML  

    Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

    Page(s): 364 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Planar lightwave integrated circuits with embedded actives for board and substrate level optical signal distribution

    Page(s): 376 - 385
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    This paper explores design options for planar optical interconnections integrated onto boards, discusses fabrication options for both beam turning and embedded interconnections to optoelectronic devices, describes integration processes for creating embedded planar optical interconnections, and discusses measurement results for a number of integration schemes that have been demonstrated by the authors. In the area of optical interconnections with beams coupled to and from the board, the topics covered include integrated metal-coated polymer mirrors and volume holographic gratings for optical beam turning perpendicular to the board. Optical interconnections that utilize active thin film (approximately 1-5 μm thick) optoelectronic components embedded in the board are also discussed, using both Si and high temperature FR-4 substrates. Both direct and evanescent coupling of optical signals into and out of the waveguide are discussed using embedded optical lasers and photodetectors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Chip-to-chip optoelectronics SOP on organic boards or packages

    Page(s): 386 - 397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB) |  | HTML iconHTML  

    In this paper, we demonstrate compatibility of hybrid, large-scale integration of both active and passive devices and components onto standard printed wiring boards in order to address mixed signal system-on-package (SOP)-based systems and applications. Fabrication, integration and characterization of high density passive components are presented, which includes the first time fabrication on FR-4 boards of a polymer buffer layer with nano scale local smoothness, blazed polymer surface relief gratings recorded by incoherent illumination, arrays of polymer micro lenses, and embedded bare die commercial p-i-n photodetectors. These embedded optical components are the essential building blocks toward a highly integrated SOP technology. The effort in this research demonstrates the potential for merging high-performance optical functions with traditional digital and radio frequency (RF) electronics onto large area and low-cost manufacturing methodologies for multifunction applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal modeling and performance of high heat flux SOP packages

    Page(s): 398 - 412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB) |  | HTML iconHTML  

    This paper explores the thermal challenges in advanced system-on-package (SOP) electronic structures, as well as candidate thermal solutions for these highly demanding cooling needs. The heat fluxes on the active surfaces are expected to approach 100 W/cm2. The impact of this high flux is exacerbated by the relatively low thermal conductivity of the organic materials in SOP packaging. Detailed three-dimensional (3-D) finite element simulations were used to study the temperature distributions in a typical SOP package, and to provide guidance for the development and implementation of "compact thermal models". These models were used to evaluate and compare the performance of various thermal technologies and to establish the most promising thermal management alternatives. The use of direct liquid cooling, by immersion of the components in inert, nontoxic, high dielectric strength perfluorocarbon liquids was seen to provide effective cooling over a range of anticipated SOP power dissipations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Next generation of 100-μm-pitch wafer-level packaging and assembly for systems-on-package

    Page(s): 413 - 425
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB) |  | HTML iconHTML  

    According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 μm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-μm pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final "optimum" design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with a coefficient of thermal expansion of 10 ppm/K or lower. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Intelligent SOP manufacturing

    Page(s): 426 - 437
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    Microsystems packaging is fundamentally dependent on the manufacture of microelectronic, photonic, radio frequency (RF), and MEMS devices. The system-on-package (SOP) approach has been identified as a key strategy for integrating these strategic packaging technologies. Because of rising costs, the challenge before SOP manufacturers is to offset capital investment with greater automation and technological innovation in the fabrication process. To reduce manufacturing cost, several important subtasks have emerged, including increasing fabrication yield, reducing product cycle time, maintaining consistent levels of product quality and performance, and improving the reliability of processing equipment. Because of the large number of steps involved, maintaining product quality in an SOP manufacturing facility requires the control of hundreds of process variables. The interdependent issues of high yield, high quality, and low cycle time are addressed by the ongoing development of several critical capabilities in state-of-the-art computer-integrated manufacturing (CIM) systems: in situ process monitoring, process/equipment modeling, real-time process control, and equipment diagnosis. Recently, the use of computational intelligence in various manufacturing applications has increased, and the SOP manufacturing arena is no exception to this trend. Artificial neural networks, genetic algorithms (GAs), and other techniques have emerged as powerful tools for assisting CIM systems in performing various process monitoring, modeling, and control functions. This paper reviews current research in these areas, as well as the potential for deployment of these capabilities in state-of-the-art SOP manufacturing facilities. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-level reliability assessment of mixed-signal convergent microsystems

    Page(s): 438 - 452
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1408 KB) |  | HTML iconHTML  

    The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 6th International Symposium on Quality Electronic Design (ISQED 2005)

    Page(s): 453
    Save to Project icon | Request Permissions | PDF file iconPDF (519 KB)  
    Freely Available from IEEE
  • 22nd ICEC—50th IEEE Holm Conference on Electrical Contacts 2004

    Page(s): 454
    Save to Project icon | Request Permissions | PDF file iconPDF (107 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering