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IEEE Micro

Issue 4 • July-Aug. 2004

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2004, Page(s): c1
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    Freely Available from IEEE
  • [Inside front cover]

    Publication Year: 2004, Page(s): c2
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  • Table of contents

    Publication Year: 2004, Page(s):2 - 3
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  • Masthead

    Publication Year: 2004, Page(s): 4
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  • Editor in Chief's Message: Saving power-Lessons from embedded systems

    Publication Year: 2004, Page(s):5 - 6
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    Freely Available from IEEE
  • FTC turns back challenge on patent coverage

    Publication Year: 2004, Page(s):7 - 86
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  • Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems

    Publication Year: 2004, Page(s):8 - 9
    Cited by:  Papers (5)
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  • Efficient real-time concurrency on low-cost microcontrollers

    Publication Year: 2004, Page(s):10 - 22
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    Advanced compiler methods squeeze more-efficient concurrency from generic processors, extending their reach and reducing the need for dedicated logic such as ASICs and FPGAs. Software thread integration creates implicitly multithreaded functions, which improves performance and enables more sophisticated programs on less expensive processors. View full abstract»

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  • Computer Society Information

    Publication Year: 2004, Page(s): 23
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  • QoS for high-performance SMT processors in embedded systems

    Publication Year: 2004, Page(s):24 - 31
    Cited by:  Papers (16)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    Although simultaneous multithreading processors provide a good cost-performance tradeoff, they exhibit unpredictable performance in real-time applications. We present a resource management scheme that eliminates a major cause of performance unpredictability in SMTs, making them suitable for many types of embedded systems. View full abstract»

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  • Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1

    Publication Year: 2004, Page(s):33 - 41
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution. View full abstract»

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  • Programming models for hybrid FPGA-cpu computational components: a missing link

    Publication Year: 2004, Page(s):42 - 53
    Cited by:  Papers (52)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    Emerging hybrid chips containing cpu and FPGA components are an exciting new development promising commercial off-the-shelf economies of scale, while also supporting hardware customization. View full abstract»

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  • Design space exploration for real-time embedded stream processors

    Publication Year: 2004, Page(s):54 - 66
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    We explore tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units' organization and utilization. The exploration methodology is applicable to all embedded-processor designs in s... View full abstract»

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  • XDSPCORE: a compiler-based configurable digital signal processor

    Publication Year: 2004, Page(s):67 - 78
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    XDSPCORE is a digital signal processor (DSP) architecture that enables time- and space-efficient execution of typical digital signal applications written in high-level languages. Our evaluation shows that the corresponding compiler can use all the DSP features as efficiently as a programmer coding in assembly language. View full abstract»

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  • The diamond-wafer paradox: a modern mystery

    Publication Year: 2004, Page(s):79 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    There is a paradoxical connection between economic growth and old electronic gadgets. It is paradoxical because wealth is usually associated with accumulating durable goods, not turning them into paper weights in an attic. This is called diamond-wafer paradox. Specifically, in growing modern economies, goods embedded with silicon wafers lose their value much faster than other durable goods or jewe... View full abstract»

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  • Micro News

    Publication Year: 2004, Page(s): 82
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  • Attacking complexity

    Publication Year: 2004, Page(s): 88
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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center