By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 9 • Sept. 2004

Filter Results

Displaying Results 1 - 15 of 15
  • Table of contents

    Publication Year: 2004, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (47 KB)
    Freely Available from IEEE
  • Operation-centric hardware description and synthesis

    Publication Year: 2004, Page(s):1277 - 1288
    Cited by:  Papers (17)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    The operation-centric hardware abstraction is useful for describing systems whose behavior exhibits a high degree of concurrency. In the operation-centric style, the behavior of a system is described as a collection of operations on a set of state elements. Each operation is specified as a predicate and a set of simultaneous state-element updates, which may only take effect in case the predicate i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test set embedding for deterministic BIST using a reconfigurable interconnection network

    Publication Year: 2004, Page(s):1289 - 1305
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB) | HTML iconHTML

    We present a new approach for deterministic built-in self-test (BIST) in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudorandom BIST to reduce correlation between ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ring generators - new devices for embedded test applications

    Publication Year: 2004, Page(s):1306 - 1320
    Cited by:  Papers (52)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB) | HTML iconHTML

    This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformatio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

    Publication Year: 2004, Page(s):1321 - 1337
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1688 KB) | HTML iconHTML

    In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than ±50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Retiming for wire pipelining in system-on-chip

    Publication Year: 2004, Page(s):1338 - 1345
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    At the integration scale of system-on-chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simple metric for slew rate of RC circuits based on two circuit moments

    Publication Year: 2004, Page(s):1346 - 1354
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    In this paper, we introduce a simple metric for the slew rate of an RC circuit based on the first two circuit moments. Metrics focusing on 50% delay of RC circuits have been proposed recently that greatly improve the accuracy of the traditional Elmore delay model. However, these new models have not been applied to the determination of transition time or slew rates (e.g., 10-90% of Vdd).... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-level crosstalk defect Simulation methodology for system-on-chip interconnects

    Publication Year: 2004, Page(s):1355 - 1361
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures. Testing for crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage of existing tests and facilitate the development of new crosstalk test methodologies,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IDAP: a tool for high-level power estimation of custom array structures

    Publication Year: 2004, Page(s):1361 - 1369
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB) | HTML iconHTML

    While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the implementation-dependent array power (IDAP) estimator, that model power dissipation in SRAM-based arrays accurately based on a high-level description of the array. The mod... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A unified approach to variable voltage scheduling for nonideal DVS processors

    Publication Year: 2004, Page(s):1370 - 1377
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltage-scaling processors. Though extensive research exists in this area, current processor limitations such as time and energy transition overhead and voltage-level discretization are often dismissed as insignificant. We show that for hard real-time applications, disregarding these details can lead to suboptimal ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Probabilistic crosstalk delay estimation for ASICs

    Publication Year: 2004, Page(s):1377 - 1383
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1384
    Request permission for commercial reuse | PDF file iconPDF (520 KB)
    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (25 KB) | HTML iconHTML
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu