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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sept. 2004

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Displaying Results 1 - 15 of 15
  • Table of contents

    Publication Year: 2004 , Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004 , Page(s): c2
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  • Operation-centric hardware description and synthesis

    Publication Year: 2004 , Page(s): 1277 - 1288
    Cited by:  Papers (14)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    The operation-centric hardware abstraction is useful for describing systems whose behavior exhibits a high degree of concurrency. In the operation-centric style, the behavior of a system is described as a collection of operations on a set of state elements. Each operation is specified as a predicate and a set of simultaneous state-element updates, which may only take effect in case the predicate is true on the current state values. The effect of an operation's state updates is atomic, that is, the legal behaviors of the system constitute some sequential interleaving of the operations. This atomic and sequential execution semantics permits each operation to be formulated as if the rest of the system were frozen and thus simplifies the description of concurrent systems. This paper presents an approach to synthesize an efficient synchronous digital implementation from an operation-centric hardware-design description. The resulting implementation carries out multiple operations per clock cycle and yet maintains the semantics that is consistent with the atomic and sequential execution of operations. The paper defines, and then gives algorithms to identify, conflict-free and sequentially composable operations that can be performed in the same clock cycle. The paper further gives an algorithm to generate the hardwired arbitration logic to coordinate the concurrent execution of conflict-free and sequentially composable operations. Lastly, the paper evaluates synthesis results based on the TRAC compiler for the TRSPEC operation-centric hardware-description language. The results from a pipelined processor example show that an operation-centric framework offers a significant reduction in design time, while achieving comparable implementation quality as traditional register-transfer-level design flows. View full abstract»

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  • Test set embedding for deterministic BIST using a reconfigurable interconnection network

    Publication Year: 2004 , Page(s): 1289 - 1305
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB) |  | HTML iconHTML  

    We present a new approach for deterministic built-in self-test (BIST) in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudorandom BIST to reduce correlation between the test data bits that are fed into the scan chains. The connections between the linear-feedback shift-register (LFSR) and the scan chains can be dynamically changed (reconfigured) during a test session. In this way, the RIN is used to match the LFSR outputs to the test cubes in a deterministic test set. The control data bits used for reconfiguration ensure that all the deterministic test cubes are embedded in the test patterns applied to the CUT. The proposed approach requires very little hardware overhead, only a modest amount of CPU time, and fewer control bits compared to the storage required for reseeding techniques or for hybrid BIST. Moreover, as a nonintrusive BIST solution, it does not require any circuit redesign and has minimal impact on circuit performance. View full abstract»

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  • Ring generators - new devices for embedded test applications

    Publication Year: 2004 , Page(s): 1306 - 1320
    Cited by:  Papers (40)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB) |  | HTML iconHTML  

    This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformations in a certain order, the resultant circuits feature a significantly reduced the number of levels of XOR logic, minimized internal fanouts, and simplified circuit layout and routing, as compared to previous schemes based on external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. Consequently, the proposed devices can operate at higher speeds than those of conventional solutions and become highly modular structures. View full abstract»

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  • A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

    Publication Year: 2004 , Page(s): 1321 - 1337
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1688 KB) |  | HTML iconHTML  

    In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than ±50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs. View full abstract»

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  • Retiming for wire pipelining in system-on-chip

    Publication Year: 2004 , Page(s): 1338 - 1345
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    At the integration scale of system-on-chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC designs. Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macroblocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate-level netlist and is formulated as a wire-retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results showed the benefits and effectiveness of our approach. View full abstract»

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  • A simple metric for slew rate of RC circuits based on two circuit moments

    Publication Year: 2004 , Page(s): 1346 - 1354
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    In this paper, we introduce a simple metric for the slew rate of an RC circuit based on the first two circuit moments. Metrics focusing on 50% delay of RC circuits have been proposed recently that greatly improve the accuracy of the traditional Elmore delay model. However, these new models have not been applied to the determination of transition time or slew rates (e.g., 10-90% of Vdd). We study how well existing approaches to 50% delay modeling translate to slew-rate modeling. We first describe a new metric called slew with two moments (S2M) that is based on Elmore's observation that the transition time of a step response is proportional to the standard deviation of the corresponding impulse response. The S2M metric modifies Elmore's original formulation by deriving a new constant of proportionality. This new constant is shown to be more accurate for general RC circuits. Next, we show that metrics relying on a simple constant multiplied by standard deviation such as S2M and Elmore do not work well for near-end nodes. To address this issue, we propose a new slew metric called scaled S2M that provides high accuracy across all types of nodes, while maintaining the advantage of a simple closed-form expression. Scaled S2M is shown to be very accurate for both near and far-end nodes. The average error for scaled S2M is approximately 2% with 96% of all nodes showing less than 5% error from a large set of industrial 0.18-μm microprocessor nets. View full abstract»

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  • High-level crosstalk defect Simulation methodology for system-on-chip interconnects

    Publication Year: 2004 , Page(s): 1355 - 1361
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures. Testing for crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage of existing tests and facilitate the development of new crosstalk test methodologies, effective crosstalk-defect coverage-analysis techniques are needed. In this paper, we present an efficient high-level crosstalk-defect simulation methodology for interconnects dominated by capacitive coupling effects. A novel coupling defect-simulation model was developed and implemented in hardware description languages. The high-level crosstalk-defect simulation methodology was examined by SPICE simulations. Experimental results show the crosstalk defect simulation methodology efficiently provides high-fidelity defect-coverage results. The proposed methodology enables fast exploration and evaluation of different tests, leading to high-quality, low-cost manufacturing tests for crosstalk-induced ac failures. View full abstract»

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  • IDAP: a tool for high-level power estimation of custom array structures

    Publication Year: 2004 , Page(s): 1361 - 1369
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementation styles. We present a methodology and a tool, the implementation-dependent array power (IDAP) estimator, that model power dissipation in SRAM-based arrays accurately based on a high-level description of the array. The models are parameterized by the array operations and various technology dependent parameters. The methodology is generic and the IDAP tool has been validated on industrial designs across a wide variety of array implementations in the e500 processor core (e500 is the Motorola processor core that is compliant with the PowerPC Book E architecture). For these industrial designs, IDAP generates high-level estimates for dynamic power dissipation that are accurate with an error margin of less than 22.2% of detailed (layout extracted) SPICE simulations. We apply the tool in three different scenarios: 1) identifying the subblocks that contribute to power significantly; 2) evaluating the effect of bitline-voltage swing on array power; and 3) evaluating the effect of memory bit-cell dimensions on array power. View full abstract»

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  • A unified approach to variable voltage scheduling for nonideal DVS processors

    Publication Year: 2004 , Page(s): 1370 - 1377
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltage-scaling processors. Though extensive research exists in this area, current processor limitations such as time and energy transition overhead and voltage-level discretization are often dismissed as insignificant. We show that for hard real-time applications, disregarding these details can lead to suboptimal or even invalid results. We propose two algorithms to account for these limitations. The first is a greedy approach, while the second is more complex, but can significantly reduce the system's energy consumption. Through experimental results on both real and randomly generated systems, we show the effectiveness of both algorithms and explore what conditions make it beneficial to use the complex algorithm over the basic one. View full abstract»

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  • Probabilistic crosstalk delay estimation for ASICs

    Publication Year: 2004 , Page(s): 1377 - 1383
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys normal distribution and its standard deviation is determined by the slew time of the victim along with the number of aggressor segments. The second is crosstalk delay normalized by the original delay without crosstalk, Δtpd/tpd. The Δtpd/tpd is equal to 2*CPR at the maximum, and CPR on average, regardless of victim length. The two metrics in conjunction with empirical slew distribution allows us to set the appropriate crosstalk delay budget, at the prelayout stage, for reducing the possibility of the crosstalk violation found in the postlayout verification process. View full abstract»

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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004 , Page(s): 1384
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004 , Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004 , Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu