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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 9 • Date Sept. 2004

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Displaying Results 1 - 16 of 16
  • Table of contents

    Publication Year: 2004 , Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004 , Page(s): c2
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  • Critical evaluation of SOI design guidelines

    Publication Year: 2004 , Page(s): 885 - 894
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (554 KB) |  | HTML iconHTML  

    Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise... View full abstract»

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  • A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula

    Publication Year: 2004 , Page(s): 895 - 900
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (763 KB) |  | HTML iconHTML  

    A ROM-less direct digital frequency synthesizer employing trigonometric quadruple angle formula is present in this paper. The worse case spectral purity is better than -130 dBc. The amplitude resolution is up to 13 bits, while the phase resolution is 12 bits. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each mu... View full abstract»

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  • A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

    Publication Year: 2004 , Page(s): 901 - 909
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1115 KB) |  | HTML iconHTML  

    The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to ... View full abstract»

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  • On circuit techniques to improve noise immunity of CMOS dynamic logic

    Publication Year: 2004 , Page(s): 910 - 925
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (719 KB) |  | HTML iconHTML  

    Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation o... View full abstract»

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  • High performance level conversion for dual V/sub DD/ design

    Publication Year: 2004 , Page(s): 926 - 936
    Cited by:  Papers (39)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1248 KB) |  | HTML iconHTML  

    Multi-V/sub DD/ design is an effective way to reduce power consumption, but the need for level conversion imposes delay and energy penalties that limit the potential gains. In this paper, we describe new level converting circuits that provide 10%-61% lower energy consumption at equivalent or better speeds compared to those available in the literature. Furthermore, we make the argument that level c... View full abstract»

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  • Distributed sleep transistor network for power reduction

    Publication Year: 2004 , Page(s): 937 - 946
    Cited by:  Papers (46)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    Sleep transistors are effective to reduce leakage power during standby modes. The cluster-based design was proposed to save sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and inserting a sleep transistor per cluster. In this paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than th... View full abstract»

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  • Reverse-body bias and supply collapse for low effective standby power

    Publication Year: 2004 , Page(s): 947 - 956
    Cited by:  Papers (19)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    Integrated circuits fabricated on a low-leakage process typically display lower performance due to the high threshold voltage (V/sub t/) transistors. Higher performance microprocessors sacrifice power efficiency by decreasing V/sub t/. We show that a processor built on a low V/sub t/ process can achieve the power-per-computation characteristics of one built using a high V/sub t/ process, by using ... View full abstract»

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  • High-speed VLSI architectures for the AES algorithm

    Publication Year: 2004 , Page(s): 957 - 967
    Cited by:  Papers (126)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in th... View full abstract»

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  • Design and implementation of low-energy turbo decoders

    Publication Year: 2004 , Page(s): 968 - 977
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    Turbo codes have been chosen in the third generation cellular standard for high-throughput data communication. These codes achieve remarkably low bit error rates at the expense of high-computational complexity. Thus for hand held communication devices, designing energy efficient Turbo decoders is of great importance. In this paper, we present a suite of MAP-based Turbo decoding algorithms with ene... View full abstract»

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  • A behavioral synthesis system for asynchronous circuits

    Publication Year: 2004 , Page(s): 978 - 994
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (858 KB) |  | HTML iconHTML  

    Behavioral synthesis of synchronous systems is a well established and researched area. The transformation of behavioral description into a datapath and control graph, and hence, to a structural realization usually requires three fundamental steps: 1) scheduling (the mapping of behavioral operations onto time slots); 2) allocation (the mapping of the behavioral operations onto abstract functional u... View full abstract»

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  • Variable precision arithmetic circuits for FPGA-based multimedia processors

    Publication Year: 2004 , Page(s): 995 - 999
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    This brief describes new efficient variable precision arithmetic circuits for field programmable gate array (FPGA)-based processors. The proposed circuits can adapt themselves to different data word lengths, avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuits to operate in single ... View full abstract»

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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004 , Page(s): 1000
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004 , Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004 , Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu