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Electron Devices, IEEE Transactions on

Issue 9 • Date Sept. 2004

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Displaying Results 1 - 25 of 35
  • Table of contents

    Page(s): c1 - c4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): c2
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  • Investigation of ultralow leakage in MOS capacitors on 4H SiC

    Page(s): 1361 - 1365
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    Ultralow leakage current through nitrided gate oxides on 4H SiC is investigated by a novel technique in this paper. The technique utilizes capacitance-voltage (C-V) measurements to characterize the relaxation of nonequilibrium capacitance due to charge leakage in floating-gate metal-oxide-semiconductor capacitors. The C-V measurements are performed at elevated temperatures and the results are extrapolated to room temperature. The obtained values for the relaxation times are in the order of 1013 s for MOS capacitors on both n-type and p-type 4H SiC. View full abstract»

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  • A general approach for the performance assessment of nanoscale silicon FETs

    Page(s): 1366 - 1370
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    Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate control than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum confinement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a [001]-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. View full abstract»

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  • Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

    Page(s): 1371 - 1379
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    Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection. View full abstract»

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  • The role of the mercury-Si Schottky-barrier height in Ψ-MOSFETs

    Page(s): 1380 - 1384
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    Pseudo-MOSFETs (Ψ-MOSFET) are routinely used for silicon-on-insulator (SOI) material characterization, allowing threshold voltage, electron and hole mobility, doping density, oxide charge, interface trap density, etc. to be determined. The HgFET, one version of the Ψ-MOSFET, uses mercury source and drain contacts. It is a very effective SOI test structure, but its current-voltage behavior is critically dependent on the Hg-Si interface. We have investigated this interface through current-voltage measurements of HgFETs and Schottky diodes and through device modeling. We show that modest barrier height changes of 0.2 eV lead to current changes of up to three orders of magnitude. Etching the Si surface in a mild HF :H2O solution can easily change barrier heights and we attribute this behavior to Si surface passivation of dangling bonds. As this surface passivation diminishes with time, the Si surface becomes a more active generation site and the barrier height of the Hg-Si interface changes, taking on the order of 50-100 h at room temperature in air. View full abstract»

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  • A 2-D analytical solution for SCEs in DG MOSFETs

    Page(s): 1385 - 1391
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    A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs. View full abstract»

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  • Analytical percolation model for predicting anomalous charge loss in flash memories

    Page(s): 1392 - 1400
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    Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated. View full abstract»

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  • SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

    Page(s): 1401 - 1408
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    In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (Cj) has been reduced in SODEL FET, i.e., Cj (area) was ∼0.73 fF/μm2 both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient γ is also reduced to less than 0.02 V12/. Nevertheless, current drives of 886 μA/μm (Ioff=15 nA/μm) in nFET and -320 μA/μm (Ioff=10 nA/μm) in pFET have been achieved in 70-nm gate length SODEL CMOS with |Vdd|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond. View full abstract»

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  • Separation of channel backscattering coefficients in nanoscale MOSFETs

    Page(s): 1409 - 1415
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    Channel backscattering coefficients in the kBT layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the kBT layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of kBT layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory. View full abstract»

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  • The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

    Page(s): 1416 - 1423
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    In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in fT, fmax, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel. View full abstract»

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  • Mobility enhancement in dual-channel P-MOSFETs

    Page(s): 1424 - 1431
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    Hole mobility is characterized in P-MOSFETs with a layered substrate consisting of tensile strained Si cap on a compressively strained Si0.4Ge0.6 buried layer grown pseudomorphically to a relaxed Si0.7Ge0.3 virtual substrate. Besides the expected mobility enhancement in the strained Si cap and in the buried Si0.4Ge0.6 layer, a second peak in mobility versus total inversion carrier areal density curve was observed under strong inversion conditions in thin Si-cap layer samples. Qualitatively, this reversed mobility trend can be correlated to the transition of inversion conduction from the buried layer to the surface layer, but quantitative analysis reveals that the surface layer mobility in thin Si-cap samples needs to be substantially larger than that in thick-cap samples, if it can be assumed that mobility is a function of transverse field. Further analysis found that, if it is assumed that mobility is a function of inversion carrier density, measured mobility curves can be matched consistently with a single set of mobility-carrier-density relationship. View full abstract»

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  • An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n+ diodes

    Page(s): 1432 - 1440
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    Snapbacks in sustain characteristics of lateral double-diffused MOSFETs (LDMOSFETs) are caused by positive feedbacks between the turn-on of the bipolar junction transistors (BJTs) and the avalanche breakdown of the drain n-n+ diodes . Although the n-n+ diodes are thus one of the most basic parasitic devices, which play a leading role in the snapback characteristics, neither a textbook nor a paper has ever described their breakdown characteristics in depth so as to realize a simple no-snapback LDMOSFET. This paper analyzes the snapback characteristics of n-n+ diodes and their mechanisms in detail. The no-snapback theory derived from this study is applied to an advanced no-snapback LDMOSFET with a simple structure, as an improved version of the conventional no-snapback LDMOSFET , which endures the electrostatic discharge (ESD) criterion for automotive applications: 15 kV, 150 pF, and 150 Ω. View full abstract»

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  • Ultrathin Al2O3 and HfO2 gate dielectrics on surface-nitrided Ge

    Page(s): 1441 - 1447
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    We have studied ultrathin Al2O3 and HfO2 gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al2O3-Ge gate stack had a teq∼23 Å, and three orders of magnitude lower leakage current compared to SiO2. HfO2-Ge allowed even greater scaling, achieving teq∼11 Å and six orders of magnitude lower leakage current compared to SiO2. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals. View full abstract»

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  • A new weight redistribution technique for electron-electron scattering in the MC simulation

    Page(s): 1448 - 1454
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    A novel technique for the weight redistribution after the electron-electron scattering between weighted electrons in the weighted ensemble Monte Carlo simulation is proposed. By generating an additional electron after each electron-electron collision the conservation of energy, momentum and charge is guaranteed, which has not been possible in the previously reported methods. The proposed technique has been successfully applied to an ideal gas simulation. Based on the new model, the tail carrier behavior due to the electron-electron scattering in the n+-doped silicon is studied. View full abstract»

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  • Testing and diagnostics of CMOS circuits using light emission from off-state leakage current

    Page(s): 1455 - 1462
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    In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others. View full abstract»

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  • Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

    Page(s): 1463 - 1467
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    The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration. View full abstract»

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  • Double gate-MOSFET subthreshold circuit for ultralow power applications

    Page(s): 1468 - 1474
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    In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance. View full abstract»

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  • Impact of collector-base junction traps on low-frequency noise in high breakdown Voltage SiGe HBTs

    Page(s): 1475 - 1482
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    This work investigates the impact of collector-base (CB) junction traps on low-frequency noise in high breakdown voltage (HBV) SiGe HBTs. By comparing the base current and 1/f noise at the same internal emitter-base (EB) voltage of the standard breakdown voltage (SBV) and HBV devices, we show that the CB junction traps not only increase base current, but also contribute base current 1/f noise when high injection occurs. The individual 1/f noise contributions from the emitter-base junction traps and from the collector-base junction traps are separated. The dependence of the 1/f noise component on the corresponding base current component is determined, and shown to be different for the EB and CB junction traps. The dependence of the total 1/f noise on the total base current, however, remains the same before and after high injection occurs in the HBV device, which is approximately the same as that for the SBV device. The IB contribution from the CB junction recombination current needs to be modeled for accurate I-V and 1/f noise modeling. View full abstract»

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  • Compact modeling of the noise of a bipolar transistor under DC and AC current crowding conditions

    Page(s): 1483 - 1495
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    The effect of current crowding on dc, on ac, and in particular on the noise characteristic of bipolar transistors, is studied. An equivalent circuit able to model these effects is presented. General formulations to calculate current crowding in arbitrary geometries are derived. Both rectangular and circular geometries are discussed in detail. View full abstract»

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  • Influence of interface traps and surface mobility degradation on scanning capacitance microscopy measurement

    Page(s): 1496 - 1503
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    Although scanning capacitance microscopy (SCM) is based on the MOS capacitance theory, the measurement frequency is 915-MHz instead of 100 kHz to 1 MHz in conventional MOS capacitance-voltage measurement. At this high frequency, the reactance of the probe tip-to-substrate capacitance can become smaller than the series resistance of the substrate inversion layer, particularly when the surface mobility is degraded. The response of the oxide-silicon interface traps to SCM measurement is also different due to the use of a 10-kHz signal to determine dC/dV. In this paper, we compare experimental and simulation data to demonstrate the effects of interface traps and surface mobility degradation on SCM measurement. Implications on the treatment of SCM data for accurate dopant profile extraction are also presented. View full abstract»

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  • Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

    Page(s): 1504 - 1513
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    The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (RS) were used to investigate the relative contribution of each individual noise source from the base current (SIB), the collector current (SIC) and, the internal emitter and base series resistances (SVr). When the voltage noise power spectral densities SVC and SVB were measured across resistances in series with the collector and base, respectively, using a relatively large RS (∼1 MΩ), SIB was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities SVC and SVE were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low RS value, SVr was found to have the dominant noise contribution at higher bias currents. IFO was found to increase SIB, SIC, and SVr. SIB was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas SIC was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. SVr was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO. View full abstract»

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  • High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

    Page(s): 1514 - 1521
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB) |  | HTML iconHTML  

    This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20°C to 110°C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V/°C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV/°C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V/°C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits. View full abstract»

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  • Effects of a finite axial magnetic field on the beam loading of a cavity

    Page(s): 1522 - 1527
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    The effect of a finite axial magnetic field on the beam loading of a cavity is evaluated. The calculation extends Branch's classic paper on ballistic bunching in that both the conductive and susceptive components of the beam-loaded admittance are computed, for general values of axial magnetic field. Also included is a comparison of the analytic formulation with a two-dimensional particle-in-cell simulation. This paper suggests that the finite axial magnetic field used in linear beam tubes (typically exceeding 1.5 × the Brillouin field) would only modify the beam-loaded admittance by about 20%, from that computed under the assumption of an infinite axial magnetic field. View full abstract»

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  • Gate oxide reliability under ESD-like pulse stress

    Page(s): 1528 - 1532
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    The reliability of very thin gate oxide under electrostatic discharge-like pulse stress is investigated. Time-dependent dielectric breakdown of gate oxide with thicknesses ranging from 2.2 to 4.7 nm is characterized down to the nanosecond time regime. The 1/E model best fits the time-to-breakdown data. Self-heating does not need to be incorporated into the time-to-breakdown model. The oxide trap generation rate is a function of the stress pulse-width for nanosecond and microsecond stress pulses. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology