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Computers, IEEE Transactions on

Issue 7 • Date July 2004

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Displaying Results 1 - 17 of 17
  • [Front cover]

    Publication Year: 2004 , Page(s): c1
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    Freely Available from IEEE
  • [Cover 2]

    Publication Year: 2004 , Page(s): c2
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    Freely Available from IEEE
  • Fair bandwidth allocation for multicasting in networks with discrete feasible set

    Publication Year: 2004 , Page(s): 785 - 797
    Cited by:  Papers (10)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    We study fairness in allocating bandwidth for loss-tolerant real-time multicast applications. We assume that the traffic is encoded in several layers so that the network can adapt to the available bandwidth and receiver processing capabilities by varying the number of layers delivered. We consider the case where receivers cannot subscribe to fractional layers. Therefore, the network can allocate o... View full abstract»

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  • Design and analysis of a self-timed duplex communication system

    Publication Year: 2004 , Page(s): 798 - 814
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1728 KB) |  | HTML iconHTML  

    Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs are more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal tr... View full abstract»

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  • On the implementation of unreliable failure detectors in partially synchronous systems

    Publication Year: 2004 , Page(s): 815 - 828
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    Unreliable failure detectors were proposed by Chandra and Toueg as mechanisms that provide information about process failures. Chandra and Toueg defined eight classes of failure detectors, depending on how accurate this information is, and presented an algorithm implementing a failure detector of one of these classes in a partially synchronous system. This algorithm is based on all-to-all communic... View full abstract»

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  • CeRA: a router for symmetrical FPGAs based on exact routing density evaluation

    Publication Year: 2004 , Page(s): 829 - 842
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2248 KB) |  | HTML iconHTML  

    We present a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation... View full abstract»

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  • Design and optimization of large size and low overhead off-chip caches

    Publication Year: 2004 , Page(s): 843 - 855
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1264 KB) |  | HTML iconHTML  

    Large off-chip L3 caches can significantly improve the performance of memory-intensive applications. However, conventional L3 SRAM caches are facing two issues as those applications require increasingly large caches. First, an SRAM cache has a limited size due to the low density and high cost of SRAM and, thus, cannot hold the working sets of many memory-intensive applications. Second, since the t... View full abstract»

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  • PACE: a new approach to dynamic voltage scaling

    Publication Year: 2004 , Page(s): 856 - 869
    Cited by:  Papers (54)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1576 KB) |  | HTML iconHTML  

    By dynamically varying CPU speed and voltage, it is possible to save significant amounts of energy while still meeting prespecified soft or hard deadlines for tasks; numerous algorithms have been published with this goal. We show that it is possible to modify any voltage scaling algorithm to minimize energy use without affecting perceived performance and present a formula to do so optimally. Becau... View full abstract»

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  • Analytically modeling a fault-tolerant messaging protocol

    Publication Year: 2004 , Page(s): 870 - 878
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    We present a simple analytical model for communication over a discarding network using a fault-tolerant messaging protocol. Our technique is an improvement over existing methods in that it accurately models both packet retransmission and the multiple types of packets exchanged between sender and receiver in order to guarantee message delivery and idempotence. The model can be applied to any networ... View full abstract»

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  • Design and performance analysis of the generalized timed token service discipline

    Publication Year: 2004 , Page(s): 879 - 891
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (912 KB) |  | HTML iconHTML  

    Multiservice networks host heterogeneous applications, requiring different qualities of service (QoS), the coexistence of which can be efficiently accounted by employing scheduling algorithms which are capable of providing different QoS simultaneously. In a previous work, we defined a reference dual-class (DC) paradigm, according to which rate-guaranteed flows are restrained from using more than t... View full abstract»

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  • Energy efficient comparators for superscalar datapaths

    Publication Year: 2004 , Page(s): 892 - 904
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1112 KB) |  | HTML iconHTML  

    Modern superscalar datapaths use aggressive execution reordering to exploit instruction-level parallelism. Comparators, either explicit or embedded into content-addressable logic, are used extensively throughout such designs to implement several key out-of-order execution mechanisms and support the memory hierarchy. The traditional comparator designs dissipate energy on a mismatch in any bit posit... View full abstract»

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  • Group key agreement efficient in communication

    Publication Year: 2004 , Page(s): 905 - 921
    Cited by:  Papers (40)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1104 KB) |  | HTML iconHTML  

    In recent years, collaborative and group-oriented applications and protocols have gained popularity. These applications typically involve communication over open networks; security thus is naturally an important requirement. Group key management is one of the basic building blocks in securing group communication. Most prior research in group key management focused on minimizing computation overhea... View full abstract»

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  • On the nondomination of cohorts coteries

    Publication Year: 2004 , Page(s): 922 - 923
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (74 KB) |  | HTML iconHTML  

    We show that subsets of Cohorts coteries proposed in [J.-R. Jiang et al., (1997)] are nondominated (ND) k-coteries, which are candidates to achieve the highest availability when utilized to solve the distributed k-mutual exclusion problem and the distributed h-out of-k mutual exclusion problem. View full abstract»

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  • Concurrent support of multiple page sizes on a skewed associative TLB

    Publication Year: 2004 , Page(s): 924 - 927
    Cited by:  Papers (1)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    Some architecture definitions (e.g., Alpha) allow the use of multiple virtual page sizes even for a single process. Unfortunately, on current set-associative TLBs (translation lookaside buffers), pages with different sizes cannot coexist together. Thus, processors supporting multiple page sizes implement fully associative TLBs. In this research note, we show how the skewed-associative TLB can acco... View full abstract»

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  • Notice of Violation of IEEE Publication Principles [Addendum]

    Publication Year: 2004 , Page(s): 928
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (28 KB)  

    Notice of Violation of IEEE Publication Principles

    Volume 52, Number 7 (July 2003) of the IEEE Transactions on Computers contained a paper: Ramnath Duggirala, Rahul Gupta, Qing-An Zeng & Dharma P. Agrawal, "Performance Enhancements of Ad Hoc Networks with Localized Route Repair," pages 854-861.
    ... View full abstract»

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  • TC Information for authors

    Publication Year: 2004 , Page(s): c3
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    Freely Available from IEEE
  • [Back cover]

    Publication Year: 2004 , Page(s): c4
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org