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Computers, IEEE Transactions on

Issue 10 • Date Oct 1988

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Displaying Results 1 - 21 of 21
  • Timing analysis using functional analysis

    Publication Year: 1988 , Page(s): 1309 - 1314
    Cited by:  Papers (34)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A, B, and R. A is the arrival time as given by exhaustive simulation; B is the arrival time as calculated by a usual block-oriented algorithm; and R is the arrival time, that does functional analysis. It is shown that BRA. The first relation means that R is never more conservative than B and whenever the containment is proper, R is an improvement over B. The second relation means that R is correct in the sense that it will never assert a signal to be valid when it is not valid according to the ideal A. Experimental results showing how often R is an improvement over B are presented View full abstract»

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  • On subsequences of arithmetic sequences

    Publication Year: 1988 , Page(s): 1314 - 1315
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    A property of subsequences in arithmetic or decimal sequences is proved. This property has a somewhat similar counterpart for linear-feedback shift register (LFSR) sequences discovered by J.L. Massey (1969). However, it is proved in a different manner, and the limit bound is two units away from the corresponding LFSR property. This property holds for any radix, but the conditions depend somewhat on the radix View full abstract»

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  • Bounding the maximum size of a packet radio network

    Publication Year: 1988 , Page(s): 1184 - 1190
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    The author addresses the problem, arising in the topology design of packet radio networks (PRNs) which use time-division multiplexing and have a diameter constraint, of what is the maximum number nc(f,k) of users which can be contained in a diameter-k PRN with f time slots per frame. The author assumed that users cannot transmit and receive simultaneously and cannot transmit/receive more than one packet at a time. This assumption implies that no two channels accessed by the same user may be assigned the same time slot. It is shown that the problem of determining nc(f,k) is identical to the problem of determining the largest number of vertices which can be contained in an f-edge colorable directed graph with diameter k. Lower bounds on nc(f, k) for f/2, k=3, 4, 5, . . . are obtained by generating large graphs of this type. The graphs are constructed and colored by simple and fast procedures which are similar for different values of f and k. An extensive bibliography on the edge-coloring problem is included View full abstract»

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  • Dynamic fault reconfiguration in a mesh-connected MIMD environment

    Publication Year: 1988 , Page(s): 1191 - 1205
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1112 KB)  

    The near-neighbor problem is characterized by many iterations of a parallel matrix operation in which each matrix element is recomputed as a function of itself and its immediately adjacent near neighbors. Several highly parallel computer systems have been designed with the near-neighbor class of problems as the target application. As the number of processors in evolving parallel computer systems increases, the capability of fault tolerance to processor failures becomes more important. The authors show how fault tolerance can be efficiently achieved on an MIMD (multiple-instruction, multiple-data-stream) computer system for the near-neighbor problem by task redistribution. The techniques discussed minimize the extra data transfers and/or the extra computation in the system with faulty processors and links View full abstract»

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  • On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    Publication Year: 1988 , Page(s): 1273 - 1280
    Cited by:  Papers (47)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, an implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Some improvements result in both enhanced capability and significant reduction in silicon area, making it possible to build the decoder on a single chip View full abstract»

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  • Minimal mesh embeddings in binary hypercubes

    Publication Year: 1988 , Page(s): 1284 - 1285
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    The authors state and prove a result about minimal graph embeddings of meshes into hypercubes. This corrects a flaw in a previously published proof by D.W. Krumme and K.N. Venkataraman (1986) View full abstract»

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  • NC algorithms for recognizing chordal graphs and k trees

    Publication Year: 1988 , Page(s): 1178 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    The authors present parallel algorithms for recognizing the chordal graphs and k trees. Under the PRAM (parallel random-access-machine) model of computation with concurrent reading and writing allowed, these algorithms take O(log n) time and require O(n4) processors. The algorithms have a better processor bound than an independent result by A. Edenbrandt (1985) for recognizing chordal graphs in parallel using O(n3m) processors View full abstract»

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  • Totally self-checking checkers with separate internal fault indication

    Publication Year: 1988 , Page(s): 1206 - 1213
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    The design of a novel class of totally self-checking (TSC) checkers with two separate output indications EN and FN is described. FN is independent of input errors and indicates internal faults only. On the other hand, the output EN indicates input errors as well as a small number of internal faults. This design technique, while improving the maintainability of the TSC networks that locate the fault in the functional circuit or in the checker itself, also increases the correct response probability of the error indication output E N. The TSC checkers presented utilize redundant copies of a given normal TSC checker which are monitored by a TSC reduction circuit operating like a TSC vote taker. The TSC reduction circuits can be easily designed using an algebraic approach based on a two-element Boolean algebra with a more efficient set of self-checking operator blocks View full abstract»

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  • TRAM: a design methodology for high-performance, easily testable, multimegabit RAMs

    Publication Year: 1988 , Page(s): 1235 - 1250
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB)  

    An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement View full abstract»

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  • Modular decomposition of combinatorial multiple-values circuits

    Publication Year: 1988 , Page(s): 1293 - 1301
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    A decomposition approach to the modular design of multiple-valued logic functions is discussed. Systematic procedures to utilize a fixed set of building blocks from which an arbitrary function can be designed are illustrated. The building blocks are composed of T gates (multiplexers). The first step is the partitioning of all logic functions into classes. Representative building blocks for each class are then developed. Finally, optimization techniques are described that reduce the number of building blocks required in the design. This approach is, in principle, applicable to functions in any radix and will always yield a design for the target function. Examples are presented to illustrate the approach for ternary functions View full abstract»

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  • Design of self-checking sequential machines

    Publication Year: 1988 , Page(s): 1280 - 1284
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    The authors present the design of self-checking sequential machines using standard memory elements, i.e. D, T, or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D, T, and JK flip-flops and for transmitting errors from their inputs to their outputs are presented; these are shown to exist in normal operation when the design procedure is used. SR flip-flops are found not to have the properties necessary for designing self-checking sequential machines View full abstract»

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  • On embedding rectangular grids in hypercubes

    Publication Year: 1988 , Page(s): 1285 - 1288
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    The following graph-embedding question is addressed: given a two-dimensional grid and the smallest hypercube with at least as many nodes as grid points, how can one assign grid points to hypercube nodes (with at most one grid point per node) so as to keep grid neighbors near each other in the cube? An embedding scheme for an infinite class of two-dimensional grids is given that keeps grid neighbors within a distance of two apart View full abstract»

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  • On multidimensional arrays of processors

    Publication Year: 1988 , Page(s): 1306 - 1309
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    An investigation is conducted of the relationship between a rectangular mesh and a square one. Asymptotically optimal algorithms are given for simulating one type by the other. The simulation results are useful since they permit designing algorithms on one network (e.g. the square mesh) in spite of the fact that the actual machine on which these algorithms will run is different (e.g. a rectangular mesh) View full abstract»

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  • Combining queueing networks and generalized stochastic Petri nets for the solution of complex models of system behavior

    Publication Year: 1988 , Page(s): 1251 - 1268
    Cited by:  Papers (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1380 KB)  

    A technique is presented whereby queueing network models and generalized stochastic Petri nets are combined in such a way as to exploit the best features of both modeling techniques. The resulting hierarchical modeling approach is useful in the solution of complex models of system behavior. The authors have chosen two examples from the recent literature to illustrate the power and scope of this technique. They also demonstrate how folding of the generalized stochastic Petri net models for these two examples is useful in obtaining efficiently solvable, approximate models (bounding models) View full abstract»

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  • Modified-mesh connected parallel computers

    Publication Year: 1988 , Page(s): 1315 - 1321
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB)  

    The author explores modifications of a mesh-connected parallel computer for the purpose of increasing the efficiency of executing important application programs. These modifications are made by adding one or more global mesh structures to the processing array. The author shows how his modifications allow asymptotic improvements in the efficiency of executing computations having low to medium interprocessor communication requirements (e.g. tree computations, prefix computations, or finding the connected components of a graph). For computations with high interprocessor communication requirements such as sorting, the author shows that they offer no speedup. He also compares the modified mesh-connected parallel computer to other similar organization including the pyramid, the X-tree, and the mesh-of-trees View full abstract»

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  • Maximum alignment of interchangeable terminals

    Publication Year: 1988 , Page(s): 1166 - 1177
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    The authors develop a linear algorithm to maximize the number of terminals aligned across a routing channel. It is assumed that the terminals in the cells on either side of the channel are interchangeable. This algorithm has application to the routing of PLAs and other circuits with interchangeable terminals View full abstract»

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  • A functional testing method for microprocessors

    Publication Year: 1988 , Page(s): 1288 - 1293
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB)  

    A method is presented for functional testing of microprocessors. First, a control fault model at the RTL (register transfer language) level is developed. Based on this model, the authors establish testing requirements for control faults. They present two test procedures to verify the write and read sequences, and use the write and read sequences to test each instruction in the microprocessor. By utilizing k-out-of-m codes, they use fewer tests to cover more faults, thereby reducing the test generation time View full abstract»

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  • The Cambridge fast ring networking system

    Publication Year: 1988 , Page(s): 1214 - 1223
    Cited by:  Papers (32)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    A discussion is presented of the choices facing a designer as faster speeds for local area networks are contemplated. The 100-Mb/s Cambridge fast ring (CFR) is described. The ring protocol allows one of a number of fixed-size slots to be used once or repeatedly. The network design allows sets of rings to be constructed by pushing the bridge function to the lowest hardware level. Low cost and ease of use is normally achieved by design of special chips; two-chip VLSI implementation is described. This VLSI hardware forms the basis of a kit of parts from which many different network components can be constructed View full abstract»

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  • Linear feedback shift register design using cyclic codes

    Publication Year: 1988 , Page(s): 1302 - 1306
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    A design technique is given for linear-feedback shift registers (LFSR) that generate test patterns for pseudoexhaustive testing of networks with restricted output dependency. This technique is based on cyclic code theory. Examples indicate that LFSRs based on cyclic codes are easier to implement and have lower hardware overhead than LFSRs that use other linear codes View full abstract»

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  • Analytic models of cyclic service systems and their application to token-passing local networks

    Publication Year: 1988 , Page(s): 1224 - 1234
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    Using the framework of cyclic-service systems with a single server, two different token-passing models are investigated. The first model is approximate, obtaining the free-tokens cycle-time distribution on an asymmetric system with infinite capacity buffers and single-token operation. The second model is exact, yielding the cycle-time distribution of the free token on an asymmetric system with unit-capacity buffers, and single-token operation. The latter result is verified using known results for symmetric, unit-capacity buffer systems. To demonstrate the positive effects of buffering, a small variation of the unit-capacity buffering scheme is introduced. Computational results include performance measures such as throughput, utilization, loss probabilities, mean cycle times, cycle-time distributions, and a comparison of two buffering schemes View full abstract»

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  • Performance evaluation of nonrectangular multistage interconnection networks

    Publication Year: 1988 , Page(s): 1269 - 1272
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    The performance is considered of unbuffered packet-switching nonrectangular multistage interconnection networks. Performance analysis is based on a simplified model for resolution of packet contention. An approximate closed-form analytical expression for the probability of packet acceptance is derived. Blocking characteristics of nonrectangular networks are analyzed and it is shown that for large nonrectangular networks, the probability of packet acceptance does not degrade with growth of network size View full abstract»

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Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
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e-mail: pmo@computer.org