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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug. 2004

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  • Table of contents

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

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  • A divide-and-conquer algorithm for 3-D capacitance extraction

    Page(s): 1157 - 1163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    We present a divide-and-conquer algorithm to improve the three-dimensional (3-D) boundary element method (BEM) for capacitance extraction. We divide large interconnect structures into small sections, set new boundary conditions using the border for each section, solve each section, and then combine the results to derive the capacitance. The target application is critical nets, clock trees, or packages where 3-D accuracy is required. Our algorithm is a significant improvement over the traditional BEMs and their enhancements, such as the "window" method, where conductors far away are dropped, and the "shield" method where conductors hidden behind other conductors are dropped. Experimental results show that our algorithm is a magnitude faster than the traditional BEM and the window+shield method, for medium to large structures. The error of the capacitance computed by the new algorithm is within 2% for self capacitance and 7% for coupling capacitance, compared with the results obtained by solving the entire system using BEM. Furthermore, our algorithms gives accurate distributed RC, where none of the previous 3-D BEM algorithms and their enhancements can. View full abstract»

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  • Transition reduction in memory buses using sector-based encoding techniques

    Page(s): 1164 - 1174
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    In this paper, we introduce a class of irredundant low-power techniques for encoding instruction or data source words before they are transmitted over buses. The key idea is to partition the source-word space into a number of sectors with unique identifiers called sector heads. These sectors can, for example, correspond to address spaces for the code, heap, and stack segments of one or more application programs. Each source word is then dynamically mapped to the appropriate sector and is encoded with respect to the sector head. In general, the sectors may be determined a priori or can dynamically be updated based on the source word that was last encountered in that sector. These sector-based encoding techniques are quite effective in reducing the number of interpattern transitions on the bus, while incurring rather small power and delay overheads. For a computer system without an on-chip cache, the proposed techniques decrease the switching activity of data address and multiplexed address buses by an average of 55% to 67%, respectively. For a system with on-chip cache, up to 55% transition reduction is achieved on a multiplexed address bus between the internal cache and the external memory. Assuming a 10 pF per line bus capacitance, we show that, by using the proposed encoding techniques, a power reduction of up to 52% can be achieved for an external data address bus and 42% for the multiplexed bus between cache and main memory. View full abstract»

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  • Register binding-based RTL power management for control-flow intensive designs

    Page(s): 1175 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    One important way to reduce power consumption is to reduce the spurious switching activity in a circuit or circuit component, i.e., activity that is not required by its specified functionality. Given a scheduled behavior and functional unit binding, we show that spurious switching activity can be reduced through proper register binding using retentive multiplexers. Retentive multiplexers can preserve their previous select signal values in the control steps in which the select signals are don't cares. A functional unit, in which spurious switching activity is completely eliminated, is called perfectly power managed. We present a general sufficient condition for register binding to ensure a set of functional units to be perfectly power managed. This condition not only applies to data-flow intensive behaviors, but also to control-flow intensive behaviors. It leads to a straightforward power-managed (PM) register-binding algorithm, which uses this condition to preserve the previous values in the input registers of a functional unit during the states in which the unit is idle. The proposed algorithm is general and independent of the functional unit binding and scheduling algorithms. Hence, it can be easily incorporated into existing high-level synthesis systems. For the benchmarks we experimented with, an average 40.7% power reduction was achieved by our method at the cost of 6.9% average area overhead, compared to power-optimized register-transfer level circuits, which did not use PM register binding. View full abstract»

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  • Optimal integer delay-budget assignment on directed acyclic graphs

    Page(s): 1184 - 1199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB) |  | HTML iconHTML  

    Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in very large scale integrated computer-aided design flow. The objective of the delay-budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to the discreteness of the timing of the components in the libraries during design-optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay-budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay-budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on the lower and upper bounds on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied at different design tasks at different levels of abstraction. We applied our proposed optimal delay-budgeting algorithm in library mapping during datapath synthesis on a field programmable gate array (FPGA) platform, using preoptimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms the zero-slack algorithm (Nair et al. 1989) in terms of area by 10% on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to two times. View full abstract»

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  • The spectral grid method: a novel fast Schrodinger-equation solver for semiconductor nanodevice simulation

    Page(s): 1200 - 1208
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB) |  | HTML iconHTML  

    A spectral-domain method is described for solving Schrodinger's equation based on the multidomain pseudospectral method and boundary patching. The computational domain is first divided into nonoverlapping subdomains. Using the Chebyshev polynomials to represent the unknown wave function in each subdomain, the spatial derivatives are calculated with a spectral accuracy at the Chebyshev collocation points. Boundary conditions at the subdomain interfaces are then enforced to ensure the global accuracy. Numerical results demonstrate that this spectral-domain method has an exponential accuracy and is flexible, and thus is an attractive method for large-scale problems. With only about four cells per wavelength, the results have an error less than 1% in our typical examples. For a typical quantum well, the method is about 51 and 295 times faster than the second-order finite-difference method for 1% and 0.1% accuracy, respectively. The spectral grid method has also been validated by results obtained by the finite-element method, semianalytical (Airy function) method, and the Numerov's method. View full abstract»

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  • Efficient simulation of coupled circuit-field problems: generalized Falk method

    Page(s): 1209 - 1219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    The proposed generalized Falk (GF) method offers an extremely simple and convenient way to solve coupled circuit-field problems in circuit simulators by transforming the discretized governing-field equations into guaranteed stable-and-passive one-dimensional (1D) equivalent-circuit systems, which are then combined with the circuit part of the overall coupled problem. More efficient than the traditional Lanczos-type methods, the GF method transforms a general finite-element system represented by a system of full matrices into an identity capacitance (mass) matrix and a tridiagonal conductance (stiffness) matrix. No positive poles are produced; all transformed matrices remain positive definite. The resulting 1D equivalent-circuit system contains only resistors, capacitors, inductors, and current sources. Several numerical examples are provided. View full abstract»

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  • Fault testing for reversible circuits

    Page(s): 1220 - 1230
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust implementation. We consider the test-set generation problem. Reversibility affects the testing problem in fundamental ways, making it significantly simpler than for the irreversible case. For example, we show that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck-at faults. We present efficient test-set constructions for the standard stuck-at fault model, as well as the usually intractable cell-fault model. We also give a practical test-set generation algorithm, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation. View full abstract»

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  • Statistical clock skew analysis considering intradie-process variations

    Page(s): 1231 - 1242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intradie process variations. We first present a formal model of the statistical clock-skew problem and then propose an algorithm based on propagation of joint probability density functions in a bottom-up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear runtime with the size of the clock tree. The proposed method was tested on several large clock-tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulation for accuracy comparison and demonstrate the need for statistical analysis of clock skew. View full abstract»

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  • Logic of constraints: a quantitative performance and functional constraint formalism

    Page(s): 1243 - 1255
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    In the era of billion-transistor design, it is critical to establish effective verification methodologies from the system level, all the way down to the implementations. In this paper, we introduce logic of constraints (LOC), a logic that is particularly suited to express quantitative performance constraints as well as functional constraints. We analyze the expressiveness of LOC and show that it is important and different from linear temporal logic, upon which traditional hardware assertion languages (e.g., PSL and OpenVera) are based. We propose an automatic simulation trace checking/runtime monitoring methodology that can be used to verify system designs very efficiently. Since a subset of LOC is decidable, we also discuss the formal verification approach for LOC formulas. Through several industrial case studies, we demonstrate the usefulness of the LOC formalism and the corresponding simulation and verification approach at the higher transaction level of abstraction. View full abstract»

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  • Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits

    Page(s): 1256 - 1263
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    With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear drivers cannot be totally ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Based on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis. View full abstract»

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  • Computation of signal-threshold crossing times directly from higher order moments

    Page(s): 1264 - 1276
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    This paper introduces a simple method for calculating the times at which any signal crosses a prespecified threshold voltage (e.g., 10%, 20%, 50%, etc.) directly from the moments. The method can use higher order moments to asymptotically improve the accuracy of the estimated crossing times. This technique bypasses the steps involved in calculating poles and residues to obtain time-domain information. Once q moments are calculated, only 2q, multiplications and (q-1) additions are required to determine any threshold-crossing time at a vermin node. Moreover, this technique avoids other problem such as pole instability. The final outcome of this paper is a set of empirical expressions relating the moments to different threshold-crossing times in analogy to the td=-0.693m1 formula. The presented methodology can also be used with other user defined forms of empirical expressions relating the moments to different threshold-crossing times. Several orders of approximations an presented for different threshold-crossing times, depending on the number of moments involved. For example, the worst-case error of a first- to seventh-order (single to seven moments) approximation of 50% RC delay is 1650%, 192.26%, 11.31%, 3.37%, 2.57%, 2.56%, and 1.43%, respectively. This technique is very useful to obtain information about certain signal metrics, such as delay and rise time directly without having to compute the whole time domain waveform. In addition, if the whole waveform is required it can be easily determined by interpolation between different threshold-crossing points. The presented technique works for both step and nonstep inputs, including piecewise-linear waveforms. View full abstract»

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  • IEEE Circuits and Systems Society Information

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu