IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Aug. 2004

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  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • A divide-and-conquer algorithm for 3-D capacitance extraction

    Publication Year: 2004, Page(s):1157 - 1163
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    We present a divide-and-conquer algorithm to improve the three-dimensional (3-D) boundary element method (BEM) for capacitance extraction. We divide large interconnect structures into small sections, set new boundary conditions using the border for each section, solve each section, and then combine the results to derive the capacitance. The target application is critical nets, clock trees, or pack... View full abstract»

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  • Transition reduction in memory buses using sector-based encoding techniques

    Publication Year: 2004, Page(s):1164 - 1174
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    In this paper, we introduce a class of irredundant low-power techniques for encoding instruction or data source words before they are transmitted over buses. The key idea is to partition the source-word space into a number of sectors with unique identifiers called sector heads. These sectors can, for example, correspond to address spaces for the code, heap, and stack segments of one or more applic... View full abstract»

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  • Register binding-based RTL power management for control-flow intensive designs

    Publication Year: 2004, Page(s):1175 - 1183
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    One important way to reduce power consumption is to reduce the spurious switching activity in a circuit or circuit component, i.e., activity that is not required by its specified functionality. Given a scheduled behavior and functional unit binding, we show that spurious switching activity can be reduced through proper register binding using retentive multiplexers. Retentive multiplexers can prese... View full abstract»

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  • Optimal integer delay-budget assignment on directed acyclic graphs

    Publication Year: 2004, Page(s):1184 - 1199
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB) | HTML iconHTML

    Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in very large scale integrated computer-aided design flow. The objective of the delay-budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed a... View full abstract»

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  • The spectral grid method: a novel fast Schrodinger-equation solver for semiconductor nanodevice simulation

    Publication Year: 2004, Page(s):1200 - 1208
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB) | HTML iconHTML

    A spectral-domain method is described for solving Schrodinger's equation based on the multidomain pseudospectral method and boundary patching. The computational domain is first divided into nonoverlapping subdomains. Using the Chebyshev polynomials to represent the unknown wave function in each subdomain, the spatial derivatives are calculated with a spectral accuracy at the Chebyshev collocation ... View full abstract»

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  • Efficient simulation of coupled circuit-field problems: generalized Falk method

    Publication Year: 2004, Page(s):1209 - 1219
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB) | HTML iconHTML

    The proposed generalized Falk (GF) method offers an extremely simple and convenient way to solve coupled circuit-field problems in circuit simulators by transforming the discretized governing-field equations into guaranteed stable-and-passive one-dimensional (1D) equivalent-circuit systems, which are then combined with the circuit part of the overall coupled problem. More efficient than the tradit... View full abstract»

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  • Fault testing for reversible circuits

    Publication Year: 2004, Page(s):1220 - 1230
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    Applications of reversible circuits can be found in the fields of low-power computation, cryptography, communications, digital signal processing, and the emerging field of quantum computation. Furthermore, prototype circuits for low-power applications are already being fabricated in CMOS. Regardless of the eventual technology adopted, testing is sure to be an important component in any robust impl... View full abstract»

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  • Statistical clock skew analysis considering intradie-process variations

    Publication Year: 2004, Page(s):1231 - 1242
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intradie process variations. We first pre... View full abstract»

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  • Logic of constraints: a quantitative performance and functional constraint formalism

    Publication Year: 2004, Page(s):1243 - 1255
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    In the era of billion-transistor design, it is critical to establish effective verification methodologies from the system level, all the way down to the implementations. In this paper, we introduce logic of constraints (LOC), a logic that is particularly suited to express quantitative performance constraints as well as functional constraints. We analyze the expressiveness of LOC and show that it i... View full abstract»

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  • Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits

    Publication Year: 2004, Page(s):1256 - 1263
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB) | HTML iconHTML

    With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are pre... View full abstract»

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  • Computation of signal-threshold crossing times directly from higher order moments

    Publication Year: 2004, Page(s):1264 - 1276
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1544 KB) | HTML iconHTML

    This paper introduces a simple method for calculating the times at which any signal crosses a prespecified threshold voltage (e.g., 10%, 20%, 50%, etc.) directly from the moments. The method can use higher order moments to asymptotically improve the accuracy of the estimated crossing times. This technique bypasses the steps involved in calculating poles and residues to obtain time-domain informati... View full abstract»

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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu