IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 8 • Aug. 2004

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  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems

    Publication Year: 2004, Page(s):793 - 811
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1054 KB) | HTML iconHTML

    In this paper, we present an approach to mapping and scheduling of distributed embedded systems for hard real-time applications, aiming at a minimization of the system modification cost. We consider an incremental design process that starts from an already existing system running a set of applications. We are interested in implementing new functionality such that the timing requirements are fulfil... View full abstract»

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  • Low-power instruction bus encoding for embedded processors

    Publication Year: 2004, Page(s):812 - 826
    Cited by:  Papers (25)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB) | HTML iconHTML

    This paper presents a low-power encoding framework for embedded processor instruction buses. The encoder is capable of adjusting its encoding not only to suit applications but furthermore to suit different aspects of particular program execution. It achieves this by exploiting application-specific knowledge regarding program hot-spots, and thus identifies efficient instruction transformations so a... View full abstract»

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  • Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

    Publication Year: 2004, Page(s):827 - 836
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (941 KB) | HTML iconHTML

    Most microprocessors employ the on-chip caches to bridge the performance gap between the processor and the main memory. However, the cache accesses usually contribute significantly to the total power consumption of the chip. Based on the observation that an overwhelming majority of the values written to the cache are "0", in this paper we propose a zero-aware SRAM cell with an asymmetric inverter ... View full abstract»

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  • DLS: dynamic backlight luminance scaling of liquid crystal display

    Publication Year: 2004, Page(s):837 - 846
    Cited by:  Papers (92)  |  Patents (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2724 KB) | HTML iconHTML

    Backlight systems dominate the power requirements of battery-operated hand-held devices with color thin-film transistor (TFT), liquid crystal displays (LCDs). We introduce dynamic luminance scaling of the backlight with appropriate image compensation. Dynamic backlight luminance scaling (DLS) keeps the perceived intensity or contrast of the image as close as possible to the original while achievin... View full abstract»

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  • Asynchronous gate-diffusion-input (GDI) circuits

    Publication Year: 2004, Page(s):847 - 856
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB) | HTML iconHTML

    Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2/spl times/ smaller than CMOS C-elements, 30% faster, and consume 85% less power, but certain CMOS elements are preferred when static storage is called for. A GDI bundled controller outperforms C... View full abstract»

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  • Robust interfaces for mixed-timing systems

    Publication Year: 2004, Page(s):857 - 873
    Cited by:  Papers (83)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (518 KB) | HTML iconHTML

    This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for "la... View full abstract»

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  • An orthogonal simulated annealing algorithm for large floorplanning problems

    Publication Year: 2004, Page(s):874 - 877
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    The conventional simulated annealing with some random generation mechanism using the sequence-pair topological representation in block placement and floorplanning is effective for a very small number of modules (40-50). This paper proposes an orthogonal simulated annealing algorithm (OSA) with an efficient generation mechanism (EGM) for solving large floorplanning problems. EGM samples a small num... View full abstract»

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  • A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

    Publication Year: 2004, Page(s):876 - 880
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB) | HTML iconHTML

    This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power diss... View full abstract»

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  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 881
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 882
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004, Page(s): 883
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2004, Page(s): 884
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu