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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • July 2004

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  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Skew measurements in clock distribution circuits using an analytic signal method

    Publication Year: 2004, Page(s):997 - 1009
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB) | HTML iconHTML

    This paper presents the application of a new analytic signal method for measuring several different kinds of clock skew in the clock distribution network of microprocessors. First, key terms are defined, and other existing skew measurement methods are reviewed. Then, detailed steps are given for applying the new method for measuring skew between a master and distributed clocks, between two distrib... View full abstract»

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  • Resource budgeting for Multiprocess High-level synthesis

    Publication Year: 2004, Page(s):1010 - 1019
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    This paper presents a new high-level synthesis methodology to generate optimized register-transfer level (RTL) implementations for multiprocess behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that interprocess communication and... View full abstract»

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  • SPFD-based wire removal in standard-cell and network-of-PLA circuits

    Publication Year: 2004, Page(s):1020 - 1030
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB) | HTML iconHTML

    Wire removal is a technique by which the total number of wires between individual circuit nodes is reduced, either by removing wires or replacing them with other new wires. The wire removal techniques we describe in this paper are based on both binary and multivalued sets of pairs of functions to be distinguished (SPFDs). Recently, it was shown that a design style based on a multilevel network of ... View full abstract»

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  • Tag compression for low power in dynamically customizable embedded processors

    Publication Year: 2004, Page(s):1031 - 1047
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    We present a methodology for power reduction by instruction/data cache-tag compression for low-power embedded processors. By statically analyzing the code/data memory layouts for the application hot spots, a variety of proposed schemes for effective tag-size reduction can be employed for power minimization in instruction and data caches. The schemes rely on significantly reducing the number of tag... View full abstract»

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  • A Markov chain sequence generator for power macromodeling

    Publication Year: 2004, Page(s):1048 - 1062
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    In this paper, we present a novel sequence generator based on a Markov chain (MC) model. Specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. W... View full abstract»

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  • A parallel fast Fourier transform on multipoles (FFTM) algorithm for electrostatics analysis of three-dimensional structures

    Publication Year: 2004, Page(s):1063 - 1072
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    A fast algorithm, called the fast Fourier transform on multipoles (FFTM) method, is developed for efficient solution of the integral equation in the boundary element method (BEM). This method employs the multipole and local expansions to approximate far field potentials, and uses the fast Fourier transform (FFT) to accelerate the multipole to local translation operator based on its convolution nat... View full abstract»

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  • Multilevel circuit clustering for delay minimization

    Publication Year: 2004, Page(s):1073 - 1085
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    In this paper, an effective algorithm is presented for multilevel circuit clustering for delay minimization, and is applicable to hierarchical field programmable gate arrays. With a novel graph contraction technique, which allows some crucial delay information of a lower-level clustering to be maintained in the contracted graph, our algorithm recursively divides the lower-level clustering into the... View full abstract»

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  • Area minimization of power distribution network using efficient nonlinear programming techniques

    Publication Year: 2004, Page(s):1086 - 1094
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    This paper deals with area minimization of power network for very large-scale integration designs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. During the optimization, a penalty method, conjugate gradient method, circuit sensitivity analysis, and merging adjoint networks are applied, which enables the algorithm to optimize large circuits.... View full abstract»

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  • Pseudorandom number generation with self-programmable cellular automata

    Publication Year: 2004, Page(s):1095 - 1101
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    We propose a new class of cellular automata, self-programming cellular automata (SPCA), with specific application to pseudorandom number generation. By changing a cell's state transition rules in relation to factors such as its neighboring cell's states, behavioral complexity can be increased and utilized. Interplay between the state transition neighborhood and rule selection neighborhood leads to... View full abstract»

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  • Self-referential verification for gate-level implementations of arithmetic circuits

    Publication Year: 2004, Page(s):1102 - 1112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    Verification of gate-level implementations of arithmetic circuits is challenging for a number of reasons: the existence of some hard-to-verify arithmetic operators, the use of different operand ordering, the incorporation of merged arithmetic with cross-operator implementations, and the employment of circuit transformations based on arithmetic relations. It is hence a peculiar problem that does no... View full abstract»

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  • SAT-based counterexample-guided abstraction refinement

    Publication Year: 2004, Page(s):1113 - 1123
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB) | HTML iconHTML

    We describe new techniques for model checking in the counterexample-guided abstraction-refinement framework. The abstraction phase "hides" the logic of various variables, hence considering them as inputs. This type of abstraction may lead to "spurious" counterexamples, i.e., traces that cannot be simulated on the original (concrete) machine. We check whether a counterexample is real or spurious wi... View full abstract»

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  • Second-order approximations for RLC trees

    Publication Year: 2004, Page(s):1124 - 1128
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    We propose two-pole one-zero second-order approximations for transfer functions in resistance-inductance-capacitance trees. The approximation matches the first three moments of the original transfer function. Formulas for computing step-response parameters such as delay time, rise time, overshoot, etc., are given. Simulation results show that adding the zero improves accuracy of the approximation. View full abstract»

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  • Indirect test architecture for SoC testing

    Publication Year: 2004, Page(s):1128 - 1142
    Cited by:  Papers (20)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB) | HTML iconHTML

    A generic model for test architectures in the core-based system-on-chip (SoC) designs consists of source/sink, wrapper, and test access mechanism (TAM). Current test architectures for digital cores assume a direct connection between the core and the tester. In these architectures, the tester establishes a physical link between itself and the core, such that it can directly control the core's desig... View full abstract»

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  • Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

    Publication Year: 2004, Page(s):1142 - 1153
    Cited by:  Papers (130)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capt... View full abstract»

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  • 2004 IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2004)

    Publication Year: 2004, Page(s): 1154
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 1155
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    Publication Year: 2004, Page(s): 1156
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu