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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 7 • Date July 2004

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Displaying Results 1 - 22 of 22
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Table of contents

    Publication Year: 2004, Page(s):1 - c4
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  • Another Step in the Right Direction for TVLSI

    Publication Year: 2004, Page(s): 673
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  • Guest Editorial

    Publication Year: 2004, Page(s):674 - 675
    Cited by:  Papers (1)
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  • Multiple-symbol parallel decoding for variable length codes

    Publication Year: 2004, Page(s):676 - 685
    Cited by:  Papers (24)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redunda... View full abstract»

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  • A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

    Publication Year: 2004, Page(s):686 - 691
    Cited by:  Papers (33)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB) | HTML iconHTML

    In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all encryption modes, including cipher block chaining (CBC) mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining and/or loop unrolling techniques cannot b... View full abstract»

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  • Fitted Elmore delay: a simple and accurate interconnect delay model

    Publication Year: 2004, Page(s):691 - 696
    Cited by:  Papers (44)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (281 KB) | HTML iconHTML

    In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely ef... View full abstract»

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  • Designing an asynchronous microcontroller using Pipefitter

    Publication Year: 2004, Page(s):696 - 699
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (118 KB) | HTML iconHTML

    This paper discusses how Pipefitter, a tool chain that implements a fully automated synthesis flow for asynchronous circuits, can be used to design a simple asynchronous microcontroller. The use of register transfer level (RTL)-like Verilog hardware description languages (HDL) as the input format makes the first steps of the design flow (i.e., specification and simulation) very easy for the design... View full abstract»

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  • Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

    Publication Year: 2004, Page(s):701 - 710
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (922 KB) | HTML iconHTML

    This paper describes a quadrature direct digital frequency synthesizer (QDDFS) architecture based on a new phase-to-sine conversion technique. The proposed technique uses polynomial interpolation and rotational transformation in a fine/coarse approach, achieving high-resolution output with a wide spurious-free dynamic range (SFDR). The QDDFS with this technique requires small-sized lookup tables a... View full abstract»

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  • An architecture and compiler for scalable on-chip communication

    Publication Year: 2004, Page(s):711 - 726
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1459 KB) | HTML iconHTML

    A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits ha... View full abstract»

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  • A recursive MISD architecture for pattern matching

    Publication Year: 2004, Page(s):727 - 734
    Cited by:  Papers (12)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    Many applications require searching for multiple patterns in large data streams for which there is no preprocessed index to rely on for efficient lookups. An multiple instruction stream-single data stream (MISD) VLSI architecture that is based on a recursive divide and conquer approach to pattern matching is proposed. This architecture allows searching for multiple patterns simultaneously. The pat... View full abstract»

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  • Placement constraints in floorplan design

    Publication Year: 2004, Page(s):735 - 745
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (647 KB) | HTML iconHTML

    In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like datapath alignment and I/O connection. There are several previous works focusing on some particular kinds of placement constraints. In this paper, we will present a unified method to handle all of them simultaneously, including preplace constraint, ran... View full abstract»

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  • Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses

    Publication Year: 2004, Page(s):746 - 755
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (779 KB) | HTML iconHTML

    With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM noise effects. In this paper, we show the emergence of multisource noise effects, where multiple DSM noise sources combine to produce functional and timing errors even when each separate noise source itself does not. We show the... View full abstract»

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  • Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead

    Publication Year: 2004, Page(s):756 - 765
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper. The desired hardware bound is specified as a constraint; the methodology aims at providing coverage in terms of all the circui... View full abstract»

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  • Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

    Publication Year: 2004, Page(s):766 - 775
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1280 KB) | HTML iconHTML

    In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, from a pra... View full abstract»

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  • Test data compression technique for embedded cores using virtual scan chains

    Publication Year: 2004, Page(s):775 - 781
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    This paper presents a design-for-test (DFT) technique to implement a "virtual scan chain" in a core that looks (to the system integrator) like it is shorter than the real scan chain inside the core. A core with a "virtual scan chain" is fully compatible with a core with a regular scan chain in terms of both the external test interface and tester program. The I/O pins of a core with a virtual scan ... View full abstract»

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  • Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

    Publication Year: 2004, Page(s):780 - 788
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB) | HTML iconHTML

    Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test appli... View full abstract»

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  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 789
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004, Page(s): 790
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2004, Page(s): 791
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): 792
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu