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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 6 • Date June 2004

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Displaying Results 1 - 25 of 28
  • Table of contents

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): c2
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  • A frequency compensation scheme for LDO voltage regulators

    Page(s): 1041 - 1050
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-μm CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time. View full abstract»

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  • A noise-shaped switching power supply using a delta-sigma modulator

    Page(s): 1051 - 1061
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    A technique to reduce in-band tones in switch-mode power supplies is described. It takes advantage of the noise-shaping properties of the delta-sigma (ΔΣ) modulator to eliminate the spikes normally present in switching power supplies. A framework is introduced for comparing the conventional pulsewidth modulated (PWM) controller and this approach. A buck converter test circuit is constructed that is designed for a PWM controller clocked at 200 kHz and then substituted with a ΔΣ modulator controller clocked at 400 kHz. The RMS noise power of the PWM controller is 14.9 mW compared to the rms noise power for the ΔΣ modulator of 75.85 mW measured in a 2-MHz bandwidth. Although the ΔΣ modulator rms noise power is higher, the noise floor is below the tones seen at the output of the PWM controller. A multibit ΔΣ modulator controller, however, provides a significant reduction in the spectral output of the power supply. Values of 3.75 and 0.24 mW rms noise power are observed at the output of a 2-bit and 4-bit ΔΣ modulator controller, respectively. View full abstract»

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  • One-tap wideband I/Q compensation for zero-IF filters

    Page(s): 1062 - 1074
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB) |  | HTML iconHTML  

    The I/Q imbalance is one of the performance bottlenecks in transceivers with stringent requirements imposed by applications such as 802.11a. The mismatch between the frequency responses of two analog low-pass filters, used, e.g., for channel selection in zero-IF receivers, makes this I/Q imbalance frequency dependent. Usually, frequency-dependent I/Q mismatch is estimated and corrected by adaptive techniques, which are complex to implement and may converge slowly due to noise. In this work, a simple, delay-based I/Q compensation scheme is proposed based on an extensive statistical analysis. Its digital implementation uses only two coefficients, which are tuned by a one-step two-tone error estimation. Simulations show that this hardware-efficient scheme significantly reduces the I/Q imbalance. View full abstract»

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  • Low-noise amplifier design for ultrawideband radio

    Page(s): 1075 - 1087
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    A new theoretical approach for designing a low-noise amplifier (LNA) for the ultra-wideband (UWB) radio is presented. Unlike narrow-band systems, the use of the noise figure (NF) performance metric becomes problematic in UWB systems because of the difficulty in defining the signal-to-noise ratio (SNR). By defining the SNR as the matched filter bound (MFB), the NF measures the degree of degradation caused by the LNA in the achievable receiver performance after the digital decoding process. The optimum noise matching network that minimizes the NF as defined above has been solved. When the narrow-band LNA assumption is made, the proposed optimum matching network simplifies to the published optimum narrow-band matching network, and the corresponding NF value also becomes equivalent. Since realizing the optimum matching network is in general difficult, an approach for designing a practical but suboptimum matching network is also presented. View full abstract»

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  • Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

    Page(s): 1088 - 1099
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs. View full abstract»

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  • SiGe HMODFET "KAIST" micropower model and amplifier realization

    Page(s): 1100 - 1105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    The recently published small-signal KAIST model is used successfully to fit the measured RF characteristics of a novel SiGe n-HMODFET device operating at micropower levels and extracted small-signal model parameters for this device under micropower operation are presented here for the first time. This model is then used to predict the performance of a simple micropower amplifier (sub 300-μW total power consumption), realized in SiGe technology, and a comparison of modeled versus measured data is included. View full abstract»

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  • Overlapped message passing for quasi-cyclic low-density parity check codes

    Page(s): 1106 - 1113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available. View full abstract»

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  • Reusable silicon IP cores for discrete wavelet transform applications

    Page(s): 1114 - 1124
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms. View full abstract»

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  • Blind channel estimation via combining autocorrelation and blind phase estimation

    Page(s): 1125 - 1131
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    Symbol spaced blind channel estimation methods are presented which can essentially use the results of any existing blind equalization method to provide a blind channel estimate of the channel. Blind equalizer's task is reduced to only phase equalization (or identification) as the channel autocorrelation is used to obtain the amplitude response of the channel. Hence, when coupled with simple algorithms such as the constant modulus algorithm (CMA) these methods at baud rate processing provide alternatives to blind channel estimation algorithms that use explicit higher order statistics (HOS) or second-order statistics (subspace) based fractionally-spaced/multichannel algorithms. The proposed methods use finite impulse response (FIR) filter linear receiver equalizer or matched filter receiver based infinite impulse response+FIR linear cascade equalizer configurations to obtain blind channel estimates. It is shown that the utilization of channel autocorrelation information together with blind phase identification of the CMA is very effective to obtain blind channel estimation. The idea of combining estimated channel autocorrelation with blind phase estimation can further be extended to improve the HOS based blind channel estimators in a way that the quality of estimates are improved. View full abstract»

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  • Family of fast linearly independent ternary arithmetic transforms

    Page(s): 1132 - 1147
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    In this paper, the family of fast linearly independent ternary arithmetic (LITA) transforms, which possesses fast forward and inverse butterfly diagrams, has been identified. This family is recursively defined and has consistent formulas relating forward and inverse transform matrices. The LITA transforms, which require horizontal or vertical permutations to have fast transforms are also discussed. Computational costs of the calculation for presented transforms are also discussed and compared with multipolarity ternary arithmetic transform for ternary benchmark functions. View full abstract»

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  • Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis

    Page(s): 1148 - 1162
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB) |  | HTML iconHTML  

    In this paper, rigorous analyses are presented for higher order multistage noise shaping (MASH) Delta-Sigma (ΔΣ) modulators, which are built out of cascaded first-order stages, with rational DC inputs and nonzero initial conditions. Asymptotic statistics such as the mean, average power, and autocorrelation of the binary quantizer error are formulated using a nonlinear difference equation approach. An important topic of interest considered here is the fractional-N phase-locked-loop frequency synthesis applications, where the input to the modulator has to be a rational constant. It has been mathematically shown that, regardless of the initial conditions, first-order and second-order MASH ΔΣ modulators with rational DC inputs cannot sufficiently randomize the quantization error samples, and, therefore, are not suitable for fractional-N synthesis applications. An irrational initial condition imposed on the first accumulator of a third or higher order MASH modulator, on the other hand, annihilates the tones throughout the whole output spectrum, and provides a very smooth noise shaping. Simulation results are provided to support the theoretically derived results. Implementation issues of the irrational initial condition in the digital domain are also discussed and investigated together with the effect of finite accumulator size on the noise-shaping quality factor. View full abstract»

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  • Saturation effects in active noise control systems

    Page(s): 1163 - 1171
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    The reference and error sensors of active noise control (ANC) systems will be saturated in real-world applications if the noise level exceeds the dynamic range of the sensors. However, there is a lack of analysis of saturation effects on the performance of ANC systems. This paper proposes an indirect method for analyzing the saturation effects in steady state using Fourier analysis. This indirect method uses clipping to approximate saturation and decomposes the saturated narrowband signal as the summation of a set of rectangular waves and a pulse-amplitude modulated signal. The theoretical analysis shows that the clipping of a sinusoidal signal produces extra odd harmonics, thus affecting the convergence speed and steady-state solution of adaptive filter in ANC systems. This analysis can be extended to narrowband noises that consist of multiple sinusoidal components such as engine noise in many ANC applications. A low-pass filter is effective in reducing saturation effects for harmonic-related noises. Analysis results are verified by computer simulations using recorded engine noise and transfer functions measured from an experimental setup. View full abstract»

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  • Real-time call admission control for packet-switched networking by cellular neural networks

    Page(s): 1172 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    In this paper, novel call admission control (CAC) algorithms are developed based on cellular neural networks. These algorithms can achieve high network utilization by performing CAC in real-time, which is imperative in supporting quality of service (QoS) communication over packet-switched networks. The proposed solutions are of basic significance in access technology where a subscriber population (connected to the Internet via an access module) needs to receive services. In this case, QoS can only be preserved by admitting those user configurations which will not overload the access module. The paper treats CAC as a set separation problem where the separation surface is approximated based on a training set. This casts CAC as an image processing task in which a complex admission pattern is to be recognized from a couple of initial points belonging to the training set. Since CNNs can implement any propagation models to explore complex patterns, CAC can then be carried out by a CNN. The major challenge is to find the proper template matrix which yields high network utilization. On the other hand, the proposed method is also capable of handling three-dimensional separation surfaces, as in a typical access scenario there are three traffic classes (e.g., two type of Internet access and one voice over asymmetric digital subscriber line. View full abstract»

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  • Bifurcation analysis of switched dynamical systems with periodically moving borders

    Page(s): 1184 - 1193
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    This paper describes a method for analyzing the bifurcation phenomena in switched dynamical systems whose switching borders are varying periodically with time. The type of systems under study covers most of power electronics circuits where two or more dynamical systems are cyclically switched according to the interaction of the state variables and some periodically moving borders. In particular, the complex bifurcation behavior of a voltage feedback buck converter is studied in detail. The analytical method developed in this paper allows bifurcation scenarios to be clearly revealed in any chosen parameter space. View full abstract»

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  • Filter bank design for a subband adaptive filtering structure with critical sampling

    Page(s): 1194 - 1202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    Subband adaptive filtering structures are attractive in applications such as acoustic echo cancellation and channel equalization, due to their properties of decorrelating the input signal and reducing the computational complexity. Recently, a new adaptive filtering structure with critical sampling was proposed. In this paper, we describe an optimization procedure to select the analysis and synthesis filter banks of this new subband structure, so that minimum steady-state mean square error or fastest convergence rate can be achieved. Such filter-bank design method is based on a theoretical analysis of the convergence properties of the adaptation algorithm and uses a nonlinear optimization routine. Computer simulations illustrate the convergence improvements that can be obtained with the filter banks designed by the proposed method. View full abstract»

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  • A lumped scalable model for silicon integrated spiral inductors

    Page(s): 1203 - 1209
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    A lumped scalable model for spiral inductors in silicon bipolar technology has been developed. The effect of three different cross sections on inductor performance was first investigated by comparing experimental measurements. Using both the results of this analysis and three-dimensional electromagnetic simulation guidelines, several circular inductors were integrated on a radial patterned ground shield for model validation purposes. The model employs a novel equation for series resistance with only one fitting parameter extracted from experimental measurements. All other model elements were related to technological and geometrical data by using rigorous analytical equations. The model was validated using one- and two-port measured performance parameters of 45 integrated inductors, and excellent agreement was found for all considered geometries up to frequencies well above self-resonance. View full abstract»

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  • Reconstruction of piecewise chaotic dynamic using a genetic algorithm multiple model approach

    Page(s): 1210 - 1222
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB) |  | HTML iconHTML  

    Reconstruction of chaotic dynamics from its time-series measurement is an important problem for many engineering applications. In this paper, we propose using a novel multiple model (MM) predictor based on a genetic algorithm (GA) to reconstruct piecewise chaotic dynamics. The motivation relies on the observation that conventional single model is usually unable to reconstruct the piecewise dynamics properly because a piecewise map is nonsmooth. In our approach, multiple radial basis function (RBF) neural predictors are used to model the piecewise dynamic in different partition intervals. Switching between different intervals could be estimated by a nonlinear gate model. In particular, a GA is employed here to train the MM and to obtain the optimal RBF parameters. Compared to conventional chaos dynamic reconstruction techniques, the proposed GA-MM method is shown to greatly improve the reconstruction performance for piecewise chaotic dynamics. The superiority is further verified by applying the GA-MM method to model the real-life radar sea-clutter signal obtained from Nova Scotia (NS), Canada, and to predict the electric power pool price time series from Alberta (AB), Canada. Both kinds of real data show that the GA-MM is effective in building a dynamical model. The proposed GA-MM method is also applied to the channel equalization problem of chaos communication systems. Based on the minimum nonlinear prediction error equalization method, it is shown that the GA-MM method has a satisfactory equalization performance even under strong channel effects. View full abstract»

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  • An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution

    Page(s): 1223 - 1233
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB) |  | HTML iconHTML  

    In this paper, a new formulation for the extraction of substrate parasitics is derived that can account for the nonuniform current distribution on contacts without contact subdivision. This method is orders of magnitude faster than the original Green's function method. The speedup is achieved by a significantly reduced matrix size combined with the application of the discrete sine transform. The method is accurate, and is well suited for large problems. View full abstract»

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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Page(s): 1235 - 1
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    Freely Available from IEEE
  • 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004)

    Page(s): 1236
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    Freely Available from IEEE
  • 2004 IEEE Asia-Pacific Conference on Circuits and Systems

    Page(s): 1237
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Page(s): 1238
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras