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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2004

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Displaying Results 1 - 22 of 22
  • [Front cover]

    Page(s): c1
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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  • Table of contents

    Page(s): 861
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  • New Associate Editor

    Page(s): 862
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  • Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

    Page(s): 863 - 870
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    CMOS transmit-receive (T/R) switches have been integrated in a 0.18-μm standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P1dB), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P1dB, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W). View full abstract»

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  • Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

    Page(s): 871 - 884
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-μm mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45° phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-MΩ load), 4-dBm IIP3 (18-dBm OIP3 to 50-Ω load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P1dB at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P1dB, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper. View full abstract»

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  • A low-power 20-GHz 52-dBΩ transimpedance amplifier in 80-nm CMOS

    Page(s): 885 - 894
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    This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dBΩ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date. View full abstract»

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  • The design of a charge-integrating modified floating-point ADC chip

    Page(s): 895 - 905
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    One of the challenges posed by calorimeters in high-energy physics experiments is digitizing wide dynamic range charge signals at high rate to a specified precision. One response to this challenge is the development of the QIE (charge integrator and encoder) concept. A QIE chip divides the input signal into multiple ranges, with each range integrating a scaled fraction of the signal. The range integrators are offset so that for any given signal magnitude, only one range will be selected as valid. The selected range integrator output is digitized to form a mantissa, and a digital code associated with that range forms an exponent. The resulting modified floating-point output format gives approximately constant measurement precision over a wide dynamic range. Floating-point converter designs are usually tailored for a specific application. A general description of the QIE concept shows how parameters are chosen to suit the application. The design of a mixed-signal chip that has been produced for a specific experiment is presented. View full abstract»

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  • A low-power half-delay-line fast skew-compensation circuit

    Page(s): 906 - 918
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB) |  | HTML iconHTML  

    A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-μm CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600∼800 MHz, as designed, with a power consumption of 25∼36 μW/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively. View full abstract»

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  • Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

    Page(s): 919 - 926
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    A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-μm ferroelectric/CMOS. View full abstract»

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  • 90% write power-saving SRAM using sense-amplifying memory cell

    Page(s): 927 - 933
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    This paper describes a low-power write scheme which reduces SRAM power by 90% by using seven-transistor sense-amplifying memory cells. By reducing the bitline swing to VDD/6 and amplifying the voltage swing by a sense-amplifier structure in a memory cell, the charging and discharging component of the power of the bit/data lines is reduced. A 64-kb test chip has been fabricated and correct read/write operation has been verified. It is also shown that the scheme can also have the capability of leakage power reduction with small modifications. Achievable leakage power reduction is estimated to be two orders of magnitude from SPICE simulation results. View full abstract»

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  • 0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

    Page(s): 934 - 940
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    We designed a logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-μW power dissipation, and 0.9-μA standby current. View full abstract»

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  • A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

    Page(s): 941 - 951
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    A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-μm DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation. View full abstract»

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  • A very low-power quadrature VCO with back-gate coupling

    Page(s): 952 - 955
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-μm triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply. View full abstract»

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  • Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier

    Page(s): 956 - 959
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    We present the design of two wide-band, low-power and low-noise amplifiers (LNAs) using SiGe BiCMOS technology. The distributed LNA demonstrated 0.1-23-GHz bandwidth and 14.5-dB gain with less than ±1-dB gain flatness. It exhibited 5-dB noise figure and 14.8-dBm output IP3, and dissipated 54-mW dc power. Comparable circuit performance was also obtained in the lumped LNA while utilizing only one-fifth the chip area of the distributed LNA. View full abstract»

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  • Gain/bandwidth programmable PA control loop for GSM/GPRS quad-band cellular handsets

    Page(s): 960 - 966
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    The analog power amplifier (PA) control loop of a fully integrated GSM/GPRS quad-band transceiver, suitable for GSM 850, GSM 900, DCS 1800, PCS 1900, and GPRS class 12 applications is presented. The control loop is based on a fully integrated PA controller (PAC) which meets applicable 3GPP GSM/GPRS specifications. Both the gain and the bandwidth of the PA control loop are programmable as well as the standby voltage delivered to the external PA: these features, together with a high driving capability (8.4 mA at 2.5 V), make this solution capable of interfacing many combinations of PAs, couplers, and detectors. The PAC has been integrated in a BiCMOS SiGe 0.35-μm process and measures 0.33 mm2. The current consumption from a single 2.8-V power supply is 2.8 mA without load and 7.2 mA in the application using Hitachi's PF08109B PA. View full abstract»

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  • An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

    Page(s): 967 - 970
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    A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias control circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The adaptive bias control circuit detects the input power level and supplies a low quiescent current of 16 mA at the low output power level and an increased current up to 90 mA according to the increased power level adaptively. The intelligent W-CDMA power amplifier using the adaptive bias circuit exhibits an improvement of average power usage efficiency of more than 1.93 times, and an adjacent channel leakage ratio by 4 dB at the output power of 28.3 dBm. View full abstract»

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  • 1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

    Page(s): 971 - 974
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    A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-μm standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dBΩ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-μA average input noise current, -17-dBm sensitivity for 10-12 bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels. View full abstract»

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  • Patent Abstracts

    Page(s): 975 - 987
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  • IEEE Solid-State Circuits Conference digital library

    Page(s): 988
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  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): c3
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  • [Blank page - back cover]

    Page(s): c4
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan