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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 6 • Date June 2004

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Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2004 , Page(s): c1 - 813
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2004 , Page(s): c2
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  • A study on global and local optimization techniques for TCAD analysis tasks

    Publication Year: 2004 , Page(s): 814 - 822
    Cited by:  Papers (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (328 KB) |  | HTML iconHTML  

    We evaluate optimization techniques to reduce the necessary user interaction for inverse modeling applications as they are used in the technology computer-aided design field. Four optimization strategies are compared. Two well-known global optimization methods, simulated annealing and genetic optimization, a local gradient-based optimization strategy, and a combination of a local and a global meth... View full abstract»

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  • Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs

    Publication Year: 2004 , Page(s): 823 - 836
    Cited by:  Papers (9)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1136 KB) |  | HTML iconHTML  

    The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improve... View full abstract»

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  • Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures

    Publication Year: 2004 , Page(s): 837 - 842
    Cited by:  Papers (32)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    This paper describes a new approach to construct a multidimensional discretization scheme of quantum drift-diffusion (QDD) model (or density gradient model) arising in MOSFET structures. The discretization is performed for the stationary QDD equations replaced by an equivalent form, employing an exponential transformation of variables. A multidimensional discretization scheme is constructed by mak... View full abstract»

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  • Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC

    Publication Year: 2004 , Page(s): 843 - 858
    Cited by:  Papers (16)  |  Patents (36)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    Composite microsystems that incorporate microelectromechanical and microelectrofluidic devices are emerging as the next generation of system-on-a-chip (SOC). We present a performance comparison between two types of microelectrofluidic systems (MEFS): continuous-flow systems and droplet-based systems. The comparison is based on a specific microelectrofluidic application-a polymerase chain reaction ... View full abstract»

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  • Probabilistic constructive optimization techniques

    Publication Year: 2004 , Page(s): 859 - 868
    Request Permissions | Click to expandAbstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    We have developed a new optimization paradigm for solving computationally intractable combinatorial optimization and synthesis problems. The technique, named probabilistic constructive, combines the advantages of both constructive and probabilistic optimization mechanisms. Since it is a constructive approach, it has a relatively short runtime and is amenable for the inclusion of insights through h... View full abstract»

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  • Synthetic circuit generation using clustering and iteration

    Publication Year: 2004 , Page(s): 869 - 887
    Cited by:  Papers (8)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (960 KB) |  | HTML iconHTML  

    The development of next-generation computer-aided design tools and field programmable gate array architectures require benchmark circuits to experiment with new algorithms and architectures. There has always been a shortage of good public benchmarks for these purposes, and even companies that have access to proprietary customer designs could benefit from designs that meet size and other particular... View full abstract»

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  • Area optimization of delay-optimized structures using intrinsic constraint graphs

    Publication Year: 2004 , Page(s): 888 - 906
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (944 KB) |  | HTML iconHTML  

    In this paper, we present a new methodology for structure optimization of block-based design. Instead of merging area and delay criteria, we segregate them into two independent steps. Solutions optimized for delay in the first step are optimized for area with a block-sizing algorithm in the second step. The fully optimized solutions eventually return to the first optimization step, if the user con... View full abstract»

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  • Efficient approximation of symbolic expressions for analog behavioral modeling and analysis

    Publication Year: 2004 , Page(s): 907 - 918
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    Efficient algorithms are presented to generate approximate expressions for transfer functions and characteristics of large linear-analog circuits. The algorithms are based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several theoretical properties of DDDs are characterized, and three algorithms, namely, based on dynamic programming... View full abstract»

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  • Efficient power profiling for battery-driven embedded system design

    Publication Year: 2004 , Page(s): 919 - 932
    Cited by:  Papers (17)  |  Patents (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (696 KB) |  | HTML iconHTML  

    The ability to efficiently and accurately estimate battery life under different design choices at the system level is an important aid in designing battery-efficient systems. Recently developed battery models help by estimating battery life under given profiles of the battery discharge current over time. However, existing techniques for energy (or average power) estimation do not provide sufficien... View full abstract»

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  • An efficient test relaxation technique for synchronous sequential circuits

    Publication Year: 2004 , Page(s): 933 - 940
    Cited by:  Papers (16)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Testing systems-on-a-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Test-set... View full abstract»

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  • Rapid method to account for process variation in full-chip capacitance extraction

    Publication Year: 2004 , Page(s): 941 - 951
    Cited by:  Papers (11)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (448 KB) |  | HTML iconHTML  

    Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacita... View full abstract»

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  • Design space exploration for optimizing on-chip communication architectures

    Publication Year: 2004 , Page(s): 952 - 961
    Cited by:  Papers (53)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    Rapid growth in the complexity of system-on-chips is being accompanied by increasing volume and diversity of on-chip communication traffic, which in turn, is driving the development of advanced system-level communication architectures. While these architectures have the potential to improve system performance, they pose significant new challenges to the system designer, owing to the complex design... View full abstract»

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  • Design of CMOS MEMS based on mechanical resonators using a RF simulation approach

    Publication Year: 2004 , Page(s): 962 - 967
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    This paper, which is mostly tutorial in nature, deals with the design of CMOS microelectromechanical systems MEMS using standard microelectronic computer-aided design tools. The proposed case study is an on-chip spectrum analyzer with an electronic mixer and a mechanical filter. Based on both analytical modeling and characterization, the filter is described using an analog hardware description lan... View full abstract»

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  • TCG-S: orthogonal coupling of P*-admissible representations for general floorplans

    Publication Year: 2004 , Page(s): 968 - 980
    Cited by:  Papers (13)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (896 KB) |  | HTML iconHTML  

    In this paper, we extend the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorplans. Each of the currently existing P*-admissible representations, sequence pair (SP), bounded-slicing grid, and transitive closure graph (TCG), has its strengths as well as weaknesses. ... View full abstract»

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  • A unified framework for generating all propagation functions for logic errors and events

    Publication Year: 2004 , Page(s): 980 - 986
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    We present a generic framework that supports efficient generation of the traditional Boolean difference function of some output with respect to any line in a combinational circuit, which is important when testing for logic defects. The framework also allows for the generation of generalized Boolean difference functions, which reflect sensitivity on event propagation from a given line to some circu... View full abstract»

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  • Computational forensic techniques for intellectual property protection

    Publication Year: 2004 , Page(s): 987 - 994
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    Computational forensic engineering (CFE) aims to identify the entity that created a particular intellectual property (IP). Specifically, our goal is to identify the synthesis tool or compiler which was used to produce a specific design or program. Rather than relying on watermarking content or designs, the generic CFE methodology analyzes the statistics of certain features of a given IP and quanti... View full abstract»

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  • 2004 IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2004)

    Publication Year: 2004 , Page(s): 995
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004 , Page(s): 996
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004 , Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2004 , Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu