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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 6 • Date June 2004

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2004, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
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  • Power minimization in QoS sensitive systems

    Publication Year: 2004, Page(s):553 - 561
    Cited by:  Papers (1)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (394 KB) | HTML iconHTML

    The majority of modern multimedia and mobile systems have two common denominators: quality-of-service (QoS) requirements, such as latency and synchronization, and strict energy constraints. However, until now no synthesis techniques have been proposed for the design and efficient use of such systems. We have two main objectives: conceptual and synthesis. The conceptual objective is to develop a ge... View full abstract»

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  • A framework for energy and transient power reduction during behavioral synthesis

    Publication Year: 2004, Page(s):562 - 572
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB) | HTML iconHTML

    In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability and efficiency. The peak power and the peak power differential drive the transient characteristics of a CMOS circuit. In this paper, we propose a framework for the simultaneous reduction of energy and transient power during behavio... View full abstract»

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  • Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

    Publication Year: 2004, Page(s):573 - 589
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (965 KB) | HTML iconHTML

    The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address the problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these ... View full abstract»

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  • Input space adaptive design: a high-level methodology for optimizing energy and performance

    Publication Year: 2004, Page(s):590 - 602
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (878 KB) | HTML iconHTML

    This paper presents a high-level design methodology, called input space adaptive design, and new design automation algorithms for optimizing energy consumption and performance. Our techniques can be applied to behaviors described in hardware description languages, predesigned register-transfer level (RTL) circuits, or in the context of traditional high-level design methodologies. An input space ad... View full abstract»

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  • Efficient metrics and high-level synthesis for dynamically reconfigurable logic

    Publication Year: 2004, Page(s):603 - 621
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1063 KB) | HTML iconHTML

    The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis (HLS) tools since it allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous works however neglect the delay of interconnects (e.g. multiplexer) which can indeed contribute heavi... View full abstract»

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  • Pel reconstruction on FPGA-augmented TriMedia

    Publication Year: 2004, Page(s):622 - 635
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB) | HTML iconHTML

    This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consi... View full abstract»

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  • Implicit deductive fault simulation for complex delay fault models

    Publication Year: 2004, Page(s):636 - 641
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults... View full abstract»

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  • Low-latency architectures for high-throughput rate Viterbi decoders

    Publication Year: 2004, Page(s):642 - 651
    Cited by:  Papers (5)
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  • An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

    Publication Year: 2004, Page(s):652 - 657
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied ... View full abstract»

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  • Efficient library characterization for high-level power estimation

    Publication Year: 2004, Page(s):657 - 661
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    This paper describes LP-DSM, which is an algorithm used for efficient library characterization in high-level power estimation. LP-DSM characterizes the power consumption of building blocks using the entropy of primary inputs and primary outputs. The experimental results showed that over a wide range of benchmark circuits implemented using full custom design in 0.35-/spl mu/m 3.3 V CMOS process the... View full abstract»

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  • Modeling subthreshold SOI logic for static timing analysis

    Publication Year: 2004, Page(s):662 - 669
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB) | HTML iconHTML

    A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pseudosaturation regions of MOS transistors operated below V/sub T/. It can be applied for predicting b... View full abstract»

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  • Erratum

    Publication Year: 2004, Page(s):669 - 670
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  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 671
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  • IEEE International Symposium on Circuits and Systems (ISCAS 2004)

    Publication Year: 2004, Page(s): 672
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2004, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu