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IEE Proceedings - Circuits, Devices and Systems

Issue 2 • Date 12 April 2004

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Displaying Results 1 - 18 of 18
  • Low-frequency noise in advanced CMOS/SOI devices

    Publication Year: 2004, Page(s):111 - 117
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1568 KB)

    The low-frequency noise (LFN) in partially- and fully-depleted SOI CMOS technologies is overviewed. The static performances and the drain current noise in both linear and saturation regimes are presented for different SOI architectures. Particular attention is paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise. T... View full abstract»

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  • Microwave noise in AlGaN/GaN channels

    Publication Year: 2004, Page(s):148 - 154
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1430 KB)

    Recent investigation of microwave noise of nominally undoped AlGaN/GaN channels is reviewed. The noise is agitated in a two-dimensional electron gas by an electric field applied in the plane of electron confinement. The experimental results are compared with those of Monte Carlo simulation and with simple semi-empirical formulas. The importance of hot-phonon effects is emphasised. View full abstract»

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  • Editorial - Noise in devices and circuits

    Publication Year: 2004, Page(s):93 - 94
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1279 KB)

    This Special Section is on 'Noise in devices and circuits' and contains expanded versions of a number of articles that were presented at the SPIE Fluctuations and Noise Symposium - Noise in Devices and Circuits, Santa Fe, New Mexico in June 2003 and were published in Proceedings of the SPIE, volume 5113. The papers in the Special Section are in the broad area of noise in devices and circuits and c... View full abstract»

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  • CMOS exponential-control variable gain amplifiers

    Publication Year: 2004, Page(s):83 - 86
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1370 KB)

    New CMOS exponential-control variable-gain amplifiers (VGAs) are presented. The control signal can be either current-mode or voltage-mode. Since no multiplier is needed in the proposed circuits, the proposed VGAs can be very compact. For the case of supply voltages VDD=|VSS|=1.5 V, the power dissipation is only 0.48 mW. The gain control range of the proposed VGA can be 30 dB.... View full abstract»

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  • Low-frequency noise and radiation response of buried oxides in SOI nMOS transistors

    Publication Year: 2004, Page(s):118 - 124
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1438 KB)

    The back channel low-frequency noise of 1.2 μm×2.3 μm SOI nMOS transistors with a buried oxide thickness of 170 nm was measured as a function of frequency, back gate bias Vbg and temperature T. For a temperature range of 85≤T≤320 K, noise measurements were performed at frequencies of 0.3≤f≤1 kHz with top gate bias Vbg=0 V and Vbg-V... View full abstract»

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  • Compact modelling of noise for RF CMOS circuit design

    Publication Year: 2004, Page(s):167 - 174
    Cited by:  Papers (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1508 KB)

    The thermal noise of short-channel NMOS transistors in a commercially available 0.13-μm CMOS technology is studied. The experimental results are modelled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parameters to the measured noise data. An essential ingredie... View full abstract»

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  • Test of data retention faults in CMOS SRAMs using special DFT circuitries

    Publication Year: 2004, Page(s):78 - 82
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1423 KB)

    Data retention faults in CMOS SRAMs are tested by sensing the voltage at the data bus lines. Sensing the voltage at one of the data bus lines with proper DFT (design for testability) reading circuitry allows the fault-free memory cells to be discriminated from the defective cell(s). Two required DFT circuitries for applying this technique are proposed. The cost of the proposed approach in terms of... View full abstract»

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  • Design of new AB2 multiplier over GF(2m) using cellular automata

    Publication Year: 2004, Page(s):88 - 92
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1396 KB)

    AB2 multiplication over GF(2m) is an essential operation in modular exponentiation, which is the basic computation for most public key cryptosystems. The authors present a new architecture that can perform AB2 multiplication over GF(2m) in m clock cycles using cellular automata. The proposed cellular automata architecture is also well suited to VLSI impl... View full abstract»

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  • Single grounded resistance tuneable sinusoidal oscillator

    Publication Year: 2004, Page(s):74 - 77
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1340 KB)

    An LC sinusoidal oscillator that requires only three transistors and some passive components is presented. Contrary to the usual method which requires the use of a variable-capacitance (varicap) diode to control the oscillation frequency value, this frequency value is controlled here through a grounded resistor. Another grounded resistor independently controls the condition of the oscillation. Mea... View full abstract»

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  • Non-quasi-static (NQS) thermal noise modelling of the MOS transistor

    Publication Year: 2004, Page(s):155 - 166
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1623 KB)

    A non-quasi-static (NQS) thermal noise model of the MOS transistor is presented that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are als... View full abstract»

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  • Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm

    Publication Year: 2004, Page(s):102 - 110
    Cited by:  Papers (28)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1477 KB)

    An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise... View full abstract»

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  • Moore's law and the energy requirement of computing versus performance

    Publication Year: 2004, Page(s):190 - 194
    Cited by:  Papers (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1366 KB)

    It has recently been recognised that speed, noise and energy dissipation are strongly interrelated entities. Following Moore's law of miniaturisation, at sizes below 40 nm, physics will impose fundamental and practical limits of performance by shrinking noise margin, increasing and quickening noise, and increasing power dissipation. It is important to locate the fundamental aspects of the problem,... View full abstract»

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  • Simulation technique for noise and timing jitter in electronic oscillators

    Publication Year: 2004, Page(s):184 - 189
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1393 KB)

    Timing jitter is a concern in high frequency oscillators; the presence of timing jitter will degrade system performance in many high speed applications. In the first part of the paper, the authors have simulated the timing jitter due to CMOS device noise in a nine-stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results... View full abstract»

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  • Review of low-frequency noise behaviour of polysilicon emitter bipolar junction transistors

    Publication Year: 2004, Page(s):125 - 137
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1574 KB)

    For many analogue integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. The authors briefly review why bipolar transistors are still of great interest and in... View full abstract»

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  • Stored-sequence sigma-delta fractional-N synthesiser

    Publication Year: 2004, Page(s):69 - 73
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1808 KB)

    The paper describes a new approach to sigma-delta fractional-N frequency synthesis based on the storage of pre-generated bitstreams. By exploiting the nature of frequency hopping systems, fabrication of a hardware sigma-delta modulator can be avoided completely and instead an optimised sigma-delta sequence for each required channel is stored in fast memory. This allows reference frequencies of sev... View full abstract»

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  • Recombination noise in semiconductor junction devices

    Publication Year: 2004, Page(s):175 - 183
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1414 KB)

    The evolution of conceptual models of recombination noise generation in bipolar semiconductor junctions is explored with particular reference to recent developments in non-classical light generation. This development is traced from the early work pioneered by van der Ziel through to recent work on sub-Poissonian light generation initiated by Yamamoto. This recent work has emphasised the importance... View full abstract»

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  • Comparison of low-frequency noise in III-V and Si/SiGe HBTs

    Publication Year: 2004, Page(s):138 - 147
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1581 KB)

    The low-frequency noise characteristics of double self-aligned InP/InGaAs and two types of Si/SiGe heterojunction bipolar transistors (HBTs) were investigated. Spectral analysis shows no striking differences; the spectra are composed of a 1/f component and the white noise is always reached at low biases. A general trend for all the transistors was the presence of Lorentzian component(s) for the sm... View full abstract»

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  • Effects of body biasing on the low frequency noise of MOSFETs from a 130 nm CMOS technology

    Publication Year: 2004, Page(s):95 - 101
    Cited by:  Papers (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1470 KB)

    The impact of body biasing on the low frequency noise (LFN) performances of MOS transistors from a 130 nm CMOS technology was investigated. The body-to-source voltage V/sub BS/ was varied from -0.5 V to +0.5 V for reverse and forward mode substrate biasing. Detailed electrical characterisation was performed and the benefits of the body bias analysed in terms of current and maximum transconductance... View full abstract»

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