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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 5 • Date May 2004

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  • Table of contents

    Publication Year: 2004 , Page(s): c1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2004 , Page(s): c2
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  • Adaptive order reduction scheme for high-order single-bit ΔΣ Modulators

    Publication Year: 2004 , Page(s): 213 - 216
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    A scheme for achieving adaptive reduction in the order of the loop filter of usual high-order, single-stage, single-bit Delta-Sigma (ΔΣ) modulators is proposed in order to improve their performance. The resulting ΔΣ modulators can recover from instability effectively, having also an extended input signal range in comparison to that of the corresponding conventional ΔΣ modulators. View full abstract»

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  • A low-latency asynchronous shift register

    Publication Year: 2004 , Page(s): 217 - 221
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed. View full abstract»

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  • MIMO systems properties preservation under SPR substitutions

    Publication Year: 2004 , Page(s): 222 - 227
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    The preservation of some control-oriented positive real properties (passivity, positivity, bounded realness, as well as input-output behavior) in multi-input multi-output transfer functions is studied, when performing substitutions (of the complex Laplace variable s) by a particular class of rational strictly positive real (SPR) functions, the so-called SPR functions of zero relative degree (SPR0 functions). We also consider here the preservation of stability properties of a class of unforced linear time-invariant systems with memoryless (possibly time-varying nonlinear) input depending on the system output. View full abstract»

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  • Corner block list representation and its application to floorplan optimization

    Publication Year: 2004 , Page(s): 228 - 233
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    We propose to use a corner block list (CBL) representation for mosaic floorplans. In a mosaic floorplan, each room has only one block assigned to it. Thus, there is a unique corner room on the top right corner of the chip. Corner block deletion and corner block insertion keep the floorplan mosaic. Through a recursive deletion process, a mosaic floorplan can be converted to a representation that is named as CBL. Given a CBL, it takes only linear time to construct the floorplan. The CBL is used for the application to very large-scale integration floorplan and building block placement. We adopt a simulated annealing process for the optimization. Soft blocks and the aspect ratio of the chip are taken into account in the optimization process. The experimental results demonstrate that the algorithm is quite promising. View full abstract»

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  • An accelerated decomposition algorithm for robust support vector Machines

    Publication Year: 2004 , Page(s): 234 - 240
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    This paper proposes an accelerated decomposition algorithm for the robust support vector machine (SVM). Robust SVM aims at solving the overfitting problem when there is outlier in the training data set, which makes the decision surface less contoured and results in sparse support vectors. Training of the robust SVM leads to a quadratic optimization problem with bound and linear constraint. Osuna provides a theorem which proves that the Standard SVM's quadratic programming (QP) problem can be broken down into a series of smaller QP subproblems. This paper derives the Kuhn-Tucker condition and decomposition algorithm for the robust SVM. Furthermore, a pre-selection technique is incorporated into the algorithm to speed up the calculation. The experiment using standard data sets shows that the accelerated decomposition algorithm makes the training process more efficient. View full abstract»

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  • Low-voltage-swing monolithic dc-dc conversion

    Publication Year: 2004 , Page(s): 241 - 248
    Cited by:  Papers (53)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-μm CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter. View full abstract»

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  • Effect of CFOA nonidealities in Miller integrator cells

    Publication Year: 2004 , Page(s): 249 - 253
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    The performance of the Miller integrator cells based on current feedback OpAmps (CFOAs) is evaluated. Inverting and noninverting structures are analyzed and compared to traditional implementations using voltage OpAmps (VOAs). Fundamental relations, useful for design purposes, are also carried out. CFOA-based implementations were found to exhibit lower dc gain and higher relative error in the unity-gain frequency, thereby, limiting the high-frequency potential. The higher CFOA bandwidth can be traded for higher quality factors. Experimental data, in excellent agreement with expected results, are included. View full abstract»

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  • An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator

    Publication Year: 2004 , Page(s): 254 - 256
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed through time sharing of the critical capacitors, i.e., the input sampling capacitor and the capacitor of the feedback digital-to-analog converter, between the I and Q channels. Circuit simulations verifying the proposed technique are presented. View full abstract»

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  • New compact CMOS continuous-time low-Voltage analog rank-order filter architecture

    Publication Year: 2004 , Page(s): 257 - 261
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-μm CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed. View full abstract»

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  • Exponential filtering for uncertain Markovian jump time-delay systems with nonlinear disturbances

    Publication Year: 2004 , Page(s): 262 - 268
    Cited by:  Papers (64)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    In this paper, we study the robust exponential filter design problem for a class of uncertain time-delay systems with both Markovian jumping parameters and nonlinear disturbances. The jumping parameters considered here are generated from a continuous-time discrete-state homogeneous Markov process, and the parameter uncertainties appearing in the state and output equations are real, time dependent, and norm bounded. The time-delay and the nonlinear disturbances are assumed to be unknown. The purpose of the problem under investigation is to design a linear, delay-free, uncertainty-independent state estimator such that, for all admissible uncertainties as well as nonlinear disturbances, the dynamics of the estimation error is stochastically exponentially stable in the mean square, independent of the time delay. We address both the filtering analysis and synthesis issues, and show that the problem of exponential filtering for the class of uncertain time-delay jump systems with nonlinear disturbances can be solved in terms of the solutions to a set of linear (quadratic) matrix inequalities. A numerical example is exploited to demonstrate the usefulness of the developed theory. View full abstract»

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  • A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

    Publication Year: 2004 , Page(s): 269 - 275
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB) |  | HTML iconHTML  

    This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply. View full abstract»

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  • IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004 , Page(s): 276
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  • 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004)

    Publication Year: 2004 , Page(s): 277
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  • 2004 IEEE Asia-Pacific Conference on Circuits and Systems

    Publication Year: 2004 , Page(s): 278
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004 , Page(s): 279
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  • Quality without compromise [advertisement]

    Publication Year: 2004 , Page(s): 280
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2004 , Page(s): c3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2004 , Page(s): c4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope